Sony CX-JV1 Service Manual page 58

CX-JV1
• VMP50 BOARD IC802 ES3889 (MPEG VIDEO/AUDIO DECODER)
Pin No. Pin Name
1, 2 GND
3 NC
4, 5 VDD
6 DSC-C
7 AUX00
8 DSCD0
9 AUX01
10 DSC-C
11 AUX02
12 DCLK
13 RST
14 AUX07
15 MUTE
16 VDD
17 MCLK
18 AUX08
19 TWS
20 AUX09
21 TSD
22 TBCK
23 PWS/SPLL1
24 RSTOUT
25, 26 GND
27, 28 NC
29 to 31 GND
32 VDD
33 RSD/SPLL0
34 AUX10
35 AUX11
36 AUX12
37 RBCK/SER IN
38 AUX13
39 AUX14
40
AUX15
41 AGND
42 VREFM
43 VREFP
44 AVDD
45 AOR+
46 AOR–
47 AOL+
58
I/O
—
Ground terminal
—
Not used
— Power supply terminal (+5V)
I
Clock signal input from the video CD MPEG processor
I
Video system select switch input terminal "L": PAL, "H": AUTO or NTSC
I/O
Two-way data bus with the video CD MPEG processor Data input from the program ROM
I Video system select switch input terminal "L": NTSC, "H": PAL or AUTO
I
Strobe signal input from the video CD MPEG processor
O
Serial data load output to the D/A converter
O
System clock signal output to the video CD MPEG processor
I Reset signal input terminal "L": reset
I
Internal status (SENSE) signal input from the digital signal processor
O
Audio muting on/off control signal output terminal Not used
—
Power supply terminal (+5V)
I Audio master clock signal input from the video CD MPEG processor
O
Laser diode on/off control signal output to the RF amplifier "L": laser diode on
I
Audio frame sync signal input from the video CD MPEG processor
I/O
Subcode Q data input from the video CD MPEG processor
I Audio data input from the video CD MPEG processor
I
Audio bit clock signal (2.8224 MHz) input from the video CD MPEG processor
Audio frame sync signal output to the video CD MPEG processor
I/O
Selection signal input terminal for the PLL clock frequency of the DCLK (pin qs) output
(fixed at "H" in this set)
O
Reset signal output to the video CD MPEG processor "L": reset
—
Ground terminal
—
Not used
—
Ground terminal
—
Power supply terminal (+5V)
Audio data output to the video CD MPEG processor
I/O
Selection signal input terminal for the PLL clock frequency of the DCLK (pin qs) output
(fixed at "L" in this set)
O Reading clock signal output to the digital signal processor
I
Interrupt request signal input from the video CD MPEG processor
I
C2 pointer signal input from the digital signal processor
Audio bit clock signal (2.8224 MHz) output to the video CD MPEG processor
I/O
Selection signal input terminal for the serial input DSC mode
"L": parallel DSC mode, "H": serial DSC mode (fixed at "L" in this set)
O
Reset signal output to the digital signal processor and motor/coil driver "L": reset
I
Subcode sync (S0+S1) detection signal input from the digital signal processor
I
Serial data input from the system controller
— Ground terminal (analog system)
I
Not used
I
Not used
—
Power supply terminal (+5V) (analog system)
O Audio data (R-ch) output to the electrical volume
O
Audio data (R-ch) output to the electrical volume
O
Audio data (L-ch) output to the electrical volume
Description