Table of Contents
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About This Guide
This document describes the basic setup, features, and operation of the ML630
Virtex®-6 FPGA HXT Optical Transmission Network (OTN) evaluation board. The ML630
board provides the hardware environment for characterizing and evaluating the GTX and
GTH transceivers available on the Virtex®-6 XC6VHX565T-2FFG1924C FPGA.
In this document Virtex-6 FPGA GTX transceiver is abbreviated as GTX transceiver.
Similarly, Virtex-6 FPGA GTH transceiver is abbreviated as GTH transceiver.
Guide Contents
This user guide contains the following chapters and appendices:
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To find additional documentation, see the Xilinx website at:
To search the Answer Database of silicon, software, and IP questions and answers, or to
create a technical support WebCase, see the Xilinx website at:
ML630 Board User Guide
UG828 (v1.0) September 28, 2011
Chapter 1, ML630 Board Features and
and operation of the ML630 Virtex-6 HXT FPGA OTN evaluation board.
Appendix A, Default Jumper
board for proper operation.
Appendix B, VITA 57.1 FMC HPC Connector
the FPGA mezzanine card (FMC) connectors.
Appendix C, ML630 Master UCF Listing for
FPGA U1 user constraints file (UCF).
Appendix D, ML630 Master UCF Listing for
FPGA U2 user constraints file (UCF).
Appendix E, ML630C Schematic Page
numbers versus the detailed description callout numbers, for easy cross-referencing.
Appendix F, Documents and
the ML630 Virtex-6 FPGA GTX Transceiver Characterization Board, and intellectual
property.
http://www.xilinx.com/support/documentation/index.htm.
http://www.xilinx.com/support.
www.xilinx.com
Operation, describes the components, features,
Positions, lists the jumpers that must be installed on the
Pinout, provides a pinout reference for
U1, provides a listing of the ML630
U2, provides a listing of the ML630
List, provides a listing of schematic page
Resources, lists documents relevant to Virtex®-6 devices,
Preface
5
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