Timing Requirements; Ddc Data; Edid Standard Compliance; X163W Edid Table - Acer X163W Service Manual

Acer
DDC signals
4.2.2
DDC signals:

4.3 Timing requirements

Scan Frequency
Horizontal
Vertical
Out of range

4.4DDC data

EDID Standard Compliance

4.4.1
EDID File Format
EDID Structure
EDID Data Table

X163W EDID table

0 1
00 FF FF FF FF FF FF 00
0
08 12
1
15 50
2
01 01
3
13 00
4
39 09
5
32 33
6
00 58
7
X163W EDID table detail description:
Address
00~07h
08~09h
Name
0A~0Bh
0C~0Fh
10h
11h
12h
13h
14h
5V@50mA TTL level
Condition
Sync polarity: (+) or (-)
Sync polarity: (+) or (-)
Excluding
Horizontal 31~57 KHz or
Vertical 56-70 Hz
panel DCLK<= 85 MHz
: VESA's EDID Standard Version #3, Revision #0,
: Version #1, Revision #3.
: See the attached table (for example)
2 3 4 5 6
01 03 08 23 14
54 33 0C 00 61
01 01 01 01 8A 21
58 C1 10 00 00 1C 00
00 0A 20 20 20
34 35 36 37 38
31 36 33 57 0A 20
Vendor Product Identification
ID information Header
ID Manufacturer
ID Product Code
ID Serial Number
Week of Manufacture
Year of Manufacture
Version Number
Revision Number
Analog/Digital Signal Level [7] Analog Signal Level
Signal Level Standard [6:5] 0.700, 0.300 (1.000Vp-p)
31 ~ 57 KHz.
56-70Hz
Message "Input Not Supported" on screen
7 8 9 A B
04 72 58 00 5C AA 80
78 E8 55 45 A3 55 4A 97
46 01 01 01 01 01
56 B0 51 00 1B 30
00 00 FD 00
20 20 20 00 00 00 FF 00
39 30 41 42 0A 00
20 20 20 20 20
ID information Header
Setup [4] No Blank -to-black Setup
8
Acer –LCD-X163W
Specification
C D E F
80
27
01 01 01
48 90
38 46 1F
31
00 00 FC
20 00 43
Description
ACR
0058
8080AA5C
08
2008
1
3