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PLL Loop Filters and Loop Parameters
of 1 and 2 works in conjunction with control on this list #14, SYSREF_GBL_PD.
26. CLKoutY_FMT: Set the clock output format for CLKoutY.
27. Clock output frequency for CLKoutX and CLKoutY.
2.1.2
TICS Pro Tips
Mousing over different controls will display a help prompt with the register address, the data bit location
and length, and a brief register description in the lower-left Context help pane.
Setting a register equal to 0 or un-checking a register's checkbox performs the same action. Similarly,
setting a register equal to 1 is the same as checking that register's checkbox.
3
PLL Loop Filters and Loop Parameters
In jitter cleaning applications that use a cascaded or dual PLL architecture, the first PLL's purpose is to
substitute the phase noise of a low-noise oscillator (VCXO) for the phase noise of a dirty reference clock.
The first PLL is typically configured with a narrow loop bandwidth to minimize the impact of the reference
clock phase noise. The reference clock consequently serves only as a frequency reference rather than a
phase reference.
The loop filters on the LMK04832EVM-CVAL evaluation board are setup using the approach above. The
loop filter for PLL1 has been configured for a narrow loop bandwidth (< 1 kHz). The specific loop
bandwidth values depend on the phase noise performance of the oscillator mounted on the board.
and
Table 3
contain the parameters for PLL1 and PLL2 for each oscillator option.
TI's PLLatinum™ Sim tool can be used to optimize PLL phase noise/jitter for given specifications. See
http://www.ti.com/tool/pllatinumsim-sw
3.1
PLL1 Loop Filter
Table 2. PLL1 Loop Filter Parameters for Crystek 122.88-MHz VCXO
Phase Margin
Loop Bandwidth
Reference Clock Frequency
Loop Filter Components
(1)
Loop Bandwidth is a function of Kφ, Kvco, N as well as loop components. Changing Kφ and N will change the loop bandwidth.
3.2
PLL2 Loop Filter
PARAMETER
LF2_C1 (C58)
LF2_C2 (C56)
C3 (internal)
C4 (internal)
LF2_R2 (R41)
R3 (internal)
R4 (internal)
Charge Pump Current, Kφ
(1)
PLL Loop Bandwidth is a function of Kφ, Kvco, N as well as loop components. Changing Kφ and N will change the loop
bandwidth.
6
LMK04832EVM-CVAL User's Guide
for more information.
122.88-MHz VCXO PLL
50˚
14 Hz
122.88 MHz
LF1_C1 (C75) = 100 nF
Table 3. Integrated VCO PLL
Copyright © 2020, Texas Instruments Incorporated
Kφ (Charge Pump)
Phase Detector Freq
VCO Gain
Output Frequency
LF1_C2 (C73) = 680 nF
(1)
LMK04832-SP
VCO0
VCO1
0.047
3.9
0.03
0.01
0.62
0.2
0.2
3.2
www.ti.com
Table 2
(1)
450 µA
1.024 MHz
2.5 kHz/V
122.88 MHz
(To PLL 2)
LF1_R2 (R64) = 39 kΩ
UNIT
nF
nF
nF
nF
kΩ
kΩ
kΩ
mA
SNAU252 – June 2020
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