Pll Loop Filters And Loop Parameters; Pll 1 Loop Filter; 122.88 Mhz Vcxo Pll - Texas Instruments LMK04816 Operating Instructions Manual

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PLL Loop Filters and Loop Parameters

In jitter cleaning applications that use a cascaded or dual PLL architecture, the first PLL‟s
purpose is to substitute the phase noise of a low-noise oscillator (VCXO or crystal resonator) for
the phase noise of a "dirty" reference clock. The first PLL is typically configured with a narrow
loop bandwidth in order to minimize the impact of the reference clock phase noise. The reference
clock consequently serves only as a frequency reference rather than a phase reference.
The loop filters on the LMK04816 evaluation board are setup using the approach above. The
loop filter for PLL1 has been configured for a narrow loop bandwidth (< 100 Hz), while the loop
filter of PLL2 has been configured for a wide loop bandwidth (> 100 kHz). The specific loop
bandwidth values depend on the phase noise performance of the oscillator mounted on the board.
The following tables contain the parameters for PLL1 and PLL2 for each oscillator option.
National‟s Clock Design Tool can be used to optimize PLL phase noise/jitter for given
specifications. See: http://www.ti.com/tool/codeloader/.

PLL 1 Loop Filter

Table 4: PLL1 Loop Filter Parameters for Crystek 122.88 MHz VCXO

122.88 MHz VCXO PLL

Kφ (Charge Pump)
49˚ 100 uA
Phase Margin
12 Hz 1.024 MHz
Loop Bandwidth Phase Detector Freq
2.5 kHz/Volt
VCO Gain
Reference Clock
122.88 MHz Output Frequency 122.88 MHz (To PLL 2)
Frequency
Loop Filter
R2_A1 = 39 kΩ
C1_A1 = 100 nF C2_A1 = 680 nF
Components
Note: PLL Loop Bandwidth is a function of K , Kvco, N as well as loop components. Changing
K and N will change the loop bandwidth.
11 SNLU107