Panasonic KX-TCD715EM Service Manual page 21

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The electrically erasable PROM PQVIT2464WM6 (IC9) is used to store all the temporary
operating parameters for the base (see
EEPROM LAYOUT (BASE
UNIT)). It uses a two-line serial
data interface with the BBIC, with bi-directional data on pin 5 (TP104), and clock on pin 6 (TP3).
6.1.5. CLOCK GENERATION (SEE Fig. 18)
A single clock generator in the BBIC uses an external crystal X1 to derive all clock frequencies
used in the base. The crystal is tuned to the exact frequency of 10.368 MHz during manufacture.
The BBIC provides a reference clock signal SYRI (pin 5, TP101) which is used to drive the PLL
circuitry in the RF module. The basic data rate for TXDA (pin 12 and RXDA (pin 20) is 1.152 Mbits
/s, which is 10.368MHz divided by 9.
6.1.6. FACTORY SERIAL PORT (SEE Fig. 18)
In order to communicate with the base band section during manufacture and servicing (using a
PC) a serial data link has been provided.
Serial data input/output is provided through the SDA terminal (J102). The data is clocked
through using the SCL terminal (J103). A ground terminal is provided by J104.
The serial port terminals J100 to J104 are connected to by means of test probe pads on the
ground plane side of the pcb.
6.1.7. AUDIO PATH-RX AUDIO-LINE INPUT (SEE Fig. 18)
Audio from the line interface TXAF (TP97) enters the BBIC on pin 134. The audio signal passes
through the analogue part of the BBIC where it is amplified and converted to a digital audio
stream signal. The burst mode controller processes this stream performing encryption and
scrambling, adding the various other fields to produce the GAP standard DECT frame,
assigning to a time slot and channel etc. to emerge on pin 12 as TXDA.
6.1.8. AUDIO PATH - TX AUDIO - LINE OUTPUT (SEE Fig. 18)
Audio from the receiver RXDA enters the BBIC on pin 20 as GAP standard DECT frames. It
passes through the decoding section burst mode controller where it separates out the frame
information and performs de-encryption and de-scrambling as required. It then goes to the DSP
where it is turned back into analogue audio. This is amplified by the analogue front end and
emerges at pin 126 - i.e. the RXAF signal of the line interface.
Circuit Diagram
21

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