Texas Instruments TAS5733L Manual

Texas Instruments TAS5733L Manual

Digital input audio power amplifier with eq and 3-band agl
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TAS5733L - Digital Input Audio Power Amplifier with EQ and 3-Band AGL
1 Features
Audio Input/Output
1
– One-Stereo Serial Audio Input
– Supports 44.1-kHz and 48-kHz Sample Rates
(LJ/RJ/I²S)
– Supports 3-Wire I²S Mode (no MCLK required)
– Automatic Audio Port Rate Detection
– Supports BTL and PBTL Configuration
– P
= 10 W @ 10% THD+N
OUT
– PVDD = 12 V, 8 Ω, 1 kHz
Audio/PWM Processing
– Independent Channel Volume Controls With
Gain of 24 dB to Mute in 0.125-dB Steps
– Programmable Three-Band Automatic Gain
Limiting (AGL)
– 20 Programmable Biquads for Speaker EQ
and Other Audio-Processing Features
General Features
– 104-dB SNR, A-Weighted, Referenced to Full
Scale (0 dB)
– I²C Serial Control Interface w/ two Addresses
– Thermal, Short-Circuit, and Undervoltage
Protection
– Up to 90% Efficient
– AD, BD, and Ternary Modulation
– PWM Level Meter
Power vs PVDD
30
RL = 4
RL = 8
25
20
15
10
5
0
8
9
10
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Sample &
Product
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15
PVDD (V)
Tools &
Technical
Software
Documents
SLASE77A – MARCH 2016 – REVISED MARCH 2016
2 Applications
LCD TV, LED TV
Low-Cost Audio Equipment
3 Description
The TAS5733L device is an efficient, digital-input
audio amplifier for driving stereo speakers configured
as a bridge tied load (BTL). In parallel bridge tied
load (PBTL) in can produce higher power by driving
the parallel outputs into a single lower impedance
load. One serial data input allows processing of up to
two discrete audio channels and seamless integration
to
most
digital
decoders. The device accepts a wide range of input
data and data rates. A fully programmable data path
routes these channels to the internal speaker drivers.
The TAS5733L device is a slave-only device
receiving all clocks from external sources. The
TAS5733L device operates with a PWM carrier
between a 384-kHz switching rate and a 288-kHz
switching rate, depending on the input sample rate.
Oversampling combined with a fourth-order noise
shaper provides a flat noise floor and excellent
dynamic range from 20 Hz to 20 kHz.
Device Information
PART NUMBER
TAS5733L
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Block Diagram
Power-On Reset
(POR)
MCLK Monitoring
and Watchdog
Serial Audio Port
MCLK
(SAP)
Digital Audio
LRCK
Sample Rate
Processor
Auto-Detect
SCLK
(DAP)
SDIN
PLL
Support &
Community
TAS5733L
audio
processors
and
(1)
PACKAGE
BODY SIZE (NOM)
HTSSOP (48)
12.50 mm × 6.10 mm
DVDD
AVDD
PVDD
Internal Voltage Supplies
Internal Regulation and Power Distribution
Open Loop Stereo
Digital to PWM
Stereo PWM Amplifier
Converter
(DPC)
Sensing & Protection
Sample Rate
2 Ch. PWM
Temperature
Converter
Modulator
Short Circuits
(SRC)
PVDD Voltage
Noise Shaping
Output Current
Click & Pop
Fault Notification
Suppression
Internal Register/State Machine Interface
I²C Control Port
SCL
SDA
PDN
RST
DR_SD
MPEG
AMP_OUT_A
AMP_OUT_B
AMP_OUT_C
AMP_OUT_D

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Summary of Contents for Texas Instruments TAS5733L

  • Page 1 Technical Community Folder Software Documents TAS5733L SLASE77A – MARCH 2016 – REVISED MARCH 2016 TAS5733L - Digital Input Audio Power Amplifier with EQ and 3-Band AGL 1 Features 2 Applications • Audio Input/Output • LCD TV, LED TV – One-Stereo Serial Audio Input •...
  • Page 2: Table Of Contents

    NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (March 2016) to Revision A Page • Moved from Product Preview to Production Data release....................Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 3: Pin Configuration And Functions

    Word select clock for the digital signal that is active on the input data line of the serial LRCLK port (1) TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 4 Doing so allows copper on the PCB to fill up to and including these pins, providing a path for heat to conduct away from the device and into the surrounding PCB area. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 5: Specifications

    (1) For operation at PVDD levels greater than 14.5 V, the modulation limit must be set to 96.1% or lower via the control port register 0x10. (2) 16.5 V is the maximum recommended voltage for continuous operation of the TAS5733L device. Testing and characterization of the device is performed up to and including 16.5 V to ensure “in system”...
  • Page 6: Thermal Characteristics

    High-level input current μA DVDD = AVDD = 3.6 V Normal mode 3.3-V supply voltage 3.3-V supply current Reset (RST = low, PDN = (DVDD, AVDD) high) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 7: Speaker Amplifier Characteristics

    = 48 KHz, R = 8 Ω, audio frequency = 1 kHz, AES17 filter, f 384 kHz, T = 25°C (unless otherwise specified). All performance is in accordance with recommended operating conditions and as tested on the TAS5733L EVM. PARAMETER TEST CONDITIONS UNIT...
  • Page 8: I²C Interface Timing Requirements

    SCLK (edge) LRCK clock edge with respect to the falling edge of SCLK –1/4 period Rise/fall time for SCLK/LRCK LRCK allowable drift before LRCK reset MCLKs Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 9 T0421-01 NOTE: On power up, hold the TAS5733L RST LOW for at least 100 μs after DVDD has reached 3 V. NOTE: If RST is asserted LOW while PDN is LOW, then RST must continue to be held LOW for at least 100 μs after PDN is deasserted (HIGH).
  • Page 10 TAS5733L SLASE77A – MARCH 2016 – REVISED MARCH 2016 www.ti.com SCLK (Input) (edge) LRCLK (Input) SDIN T0026-04 Figure 4. Serial Audio Port Timing Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 11: Typical Characteristics - Stereo Btl Mode

    PVDD = 12 V = 4 Ω PVDD = 12 V = 8 Ω Figure 9. THD+N vs Frequency - BTL Figure 10. THD+N vs Output Power - BTL Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 12 PVDD = 12 V = 8 Ω PVDD = 12 V = 4 Ω Figure 15. Crosstalk vs Frequency - BTL Figure 16. Crosstalk vs Frequency - BTL Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 13: Typical Characteristics - Mono Pbtl Mode

    PVDD = 12 V = 3 Ω PVDD = 12 V = 2 Ω Figure 21. THD+N vs Output Power - PBTL Figure 22. THD+N vs Output Power - PBTL Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 14 For instance, 40 W of total output power means 2 × 20 W, with 20 W delivered by one channel and 20 W delivered by the other channel. Figure 25. Efficiency vs Output Power - PBTL Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 15: Detailed Description

    7 Detailed Description 7.1 Overview The TAS5733L device is an efficient, digital-input audio amplifier for driving stereo speakers configured as a bridge tied load (BTL). In parallel bridge tied load (PBTL) in can produce higher power by driving the parallel outputs into a single lower impedance load.
  • Page 16: Audio Signal Processing Overview

    10 Biquads Mixer R 0x5B, 0x5C 0x42 - 0x41, 0x47 Vol 2 2 Biquads AGL 3 0x60, 0x61 Mid Band 2 Biquads Figure 28. TAS5733L Audio Process Flow Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 17: Feature Description

    7.4 Feature Description 7.4.1 Clock, Autodetection, and PLL The TAS5733L device is an I²S slave device. The TAS5733L device accepts MCLK, SCLK, and LRCK. The digital audio processor (DAP) supports all the sample rates and MCLK rates that are defined in the Clock Control Register.
  • Page 18 D1 of register 0x02. This bit can be reset only by an I²C write. Table 2. ADR/FAULT Output States ADR/FAULT DESCRIPTION Overcurrent (OC) or undervoltage (UVP) error or overtemperature error (OTE) or overvoltage error No faults (normal operation) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 19: Device Functional Modes

    150°C (nominal), the device enters thermal shutdown, where all half-bridge outputs enter the high-impedance (Hi-Z) state, and ADR/FAULT asserts low if the device is configured to function as a fault output. The TAS5733L device recovers automatically once the junction temperature of the device drops approximately 30°C.
  • Page 20: Programming

    Mono Mode 7.5.3.1 Stereo Mode Stereo mode is the most common option for the TAS5733L. TAS5733L can be connected in 2.0 mode to drive stereo channels. Detailed application section regarding the stereo mode is discussed in the Stereo Bridge Tied Load Application section.
  • Page 21 A generic data transfer sequence is shown in Figure The 7-bit address for the TAS5733L device is 0101 010 (0x54) or 0101 011 (0x56) as defined by ADR/FAULT (external pulldown for 0x54 and pullup for 0x56). 7.6.1.2 I²C Slave Address The ADR/FAULT is an input pin during power-up and after each toggle of RST, which is used to set the I²C sub-...
  • Page 22 Initially, a write is done to transfer the address byte or bytes of the internal memory address to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5733L address and the read/write bit, TAS5733L device responds with an acknowledge bit.
  • Page 23 7.6.2 Serial Interface Control and Timing 7.6.2.1 Serial Data Interface Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5733L DAP accepts serial data in 16-bit, 20-bit, or 24-bit left-justified, right-justified, and I²S serial data formats.
  • Page 24 20-Bit Mode 19 18 19 18 16-Bit Mode 15 14 15 14 T0034-01 NOTE: All data presented in two's-complement form with MSB first. Figure 37. I²S 64-f Format Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 25 16 Clks LRCLK Right Channel Left Channel SCLK SCLK 16-Bit Mode T0266-01 NOTE: All data presented in two's-complement form with MSB first. Figure 39. I²S 32-f Format Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 26 20-Bit Mode 19 18 19 18 16-Bit Mode 15 14 15 14 T0034-02 NOTE: All data presented in two's-complement form with MSB first. Figure 40. Left-Justified 64-f Format Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 27 16 Clks LRCLK Right Channel Left Channel SCLK SCLK 16-Bit Mode T0266-02 NOTE: All data presented in two's-complement form with MSB first. Figure 42. Left-Justified 32-f Format Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 28 15 14 19 18 15 14 16-Bit Mode 15 14 15 14 T0034-03 All data presented in two's-complement form with MSB first. Figure 43. Right-Justified 64-f Format Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 29 All mixer gain coefficients are 26-bit coefficients using a 3.23 number format. Numbers formatted as 3.23 numbers mean that the binary point has 3 bits to the left and 23 bits to the right. This is shown in Figure Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 30 Digit 3 Digit 2 Digit 1 u = unused or don’t care bits Digit = hexadecimal digit M0127-01 Figure 48. Alignment of 3.23 Coefficient in 32-Bit I²C Word Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 31: Register Maps

    0x30 0x1A Start/stop period register Description shown in subsequent section 0x68 0x1B Oscillator trim register Description shown in subsequent section 0x82 (1) Do not access reserved registers. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 32 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 0x2C ch1_bq[6] u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 33 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 0x35 ch2_bq[5] u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 34 AGL1 softening filter omega u[31:26], oe[25:0] 0x0078 0000 0x3C AGL1 attack rate Description shown in subsequent section 0x0000 0100 AGL1 release rate Description shown in subsequent section 0xFFFF FF00 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 35 (9.17 format) 0x0002 0000 0x58 ch1_bq[10] u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 36 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 0x62 IDF post scale Description shown in subsequent section 0x0000 0080 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 37 7.7.2 Detailed Register Descriptions 7.7.2.1 Clock Control Register (0x00) The clocks and data rates are automatically determined by the TAS5733L. The clock control register contains the autodetected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency.
  • Page 38 0x0E. If 1, use hard unmute on recovery from clock error. This is a fast recovery, a single-step volume ramp. Bits D1–D0: Select de-emphasis Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 39 (1) Default values are in bold. 7.7.2.5 Serial Data Interface Register (0x04) As shown in Table 9, the TAS5733L supports nine serial data modes. The default is 24-bit, I S mode. Table 9. Serial Data Interface Control Register (0x04) Format RECEIVE SERIAL DATA WORD D7–D4...
  • Page 40 Step size is 0.125 dB and volume registers are 2 bytes. Master volume – 0x07 (default is mute, 0x03FF) Channel-1 volume – 0x08 (default is 0 dB, 0x00C0) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 41 – – – – Volume slew 256 steps (21-ms volume ramp time at 48 kHz) – – – – – Reserved (1) Default values are in bold. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 42 (if bit D5 is set to 0 in system control register 2, 0x05). Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 43 4241.7-ms 50% duty cycle start/stop period – – – 5655.6-ms 50% duty cycle start/stop period – – – 7383.7-ms 50% duty cycle start/stop period (1) Default values are in bold. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 44 13,196.4-ms 50% duty cycle start/stop period 7.7.2.14 Oscillator Trim Register (0x1B) The TAS5733L PWM processor contains an internal oscillator to support autodetect of I S clock rates. This reduces system cost because an external reference is not required. A reference resistor must be connected...
  • Page 45 Selects which PWM channel is output to AMP_OUT_D Note that channels are encoded so that channel 1 = 0x00, channel 2 = 0x01, …, channel 4 = 0x03. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 46 – – – Multiplex channel 1 to AMP_OUT_D – – – – – – Multiplex channel 2 to AMP_OUT_D FUNCTION Reserved (1) Default values are in bold. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 47 SRC = 8 – – – – SRC = 9 – – – – Reserved – – – – – – Reserved (1) Default values are in bold. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 48 – – Configure bank 1 (32 kHz by default) – – – – – Reserved – – – – – Reserved (1) Default values are in bold. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 49: Application And Implementation

    8.1.1.2 Amplifier Output Filtering The TAS5733L device is often used with a low-pass filter, which is used to filter out the carrier frequency of the PWM modulated output. This filter is frequently referred to as the L-C Filter, due to the presence of an inductive element L and a capacitive element C to make up the 2-pole filter.
  • Page 50: Typical Applications

    The Stereo BTL Configuration is shown in Figure Figure 49. Stereo Bridge Tied Load Application Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 51 8.2.1.2.2 Control and Software Integration The TAS5733L device has a bidirectional I²C used to program the registers of the device and to read device status. The TAS5733LEVM and the PurePath Console GUI are powerful tools that allow the TAS5733L evaluation, control and configuration.
  • Page 52 Event 3 is not supported for 240 ms + 1.3 × t after trim following AVDD/DVDD power- start up ramp (where t is specified by register 0x1A). start Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 53 The Mono PBTL Configuration is shown in Figure Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 54 Figure 51. Mono Parallel Bridge Tied Load Application 8.2.2.1 Design Requirements The design requirements for the Mono Parallel Bridge Tied Load Appliction of the TAS5733L device is found in Table 26 Table 26. Design Requirements for Mono Parallel Bridge Tied Load Application...
  • Page 55: Power Supply Recommendations

    Figure 24 9 Power Supply Recommendations To facilitate system design, the TAS5733L device requires only a 3.3-V supply in addition to the PVDD power- stage supply. An internal voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only a few external capacitors.
  • Page 56: Layout

    Placement of these components too far from the TAS5733L device may cause ringing on the output pins that can cause the voltage on the output pin to exceed the maximum allowable ratings shown in the Absolute Maximum Ratings table, damaging the device.
  • Page 57: Layout Example

    10.2 Layout Example Figure 52. Layout Example (Stereo) - Top View Composite Figure 53. Layout Example (Stereo) - Top Layer Figure 54. Layout Example (Stereo) - Bottom Layer Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 58 Layout Example (continued) Figure 55. Layout Example (Mono) - Top View Composite Figure 56. Layout Example (Mono) - Top Layer Figure 57. Layout Example (Mono) - Bottom Layer Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 59: Device And Documentation Support

    SLASE77A – MARCH 2016 – REVISED MARCH 2016 11 Device and Documentation Support 11.1 Trademarks PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
  • Page 60: Mechanical, Packaging, And Orderable Information

    This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TAS5733L...
  • Page 61 Op Temp (°C) Device Marking Samples Drawing (4/5) TAS5733LDCA ACTIVE HTSSOP Green (RoHS CU NIPDAU Level-3-260C-168 HR 0 to 85 TAS5733L & no Sb/Br) TAS5733LDCAR ACTIVE HTSSOP 2000 Green (RoHS CU NIPDAU Level-3-260C-168 HR 0 to 85 TAS5733L & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
  • Page 62 PACKAGE OPTION ADDENDUM www.ti.com 1-Apr-2016 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2...
  • Page 63 PACKAGE MATERIALS INFORMATION www.ti.com 2-Apr-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Reel Reel Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) TAS5733LDCAR HTSSOP 2000 330.0 24.4 15.8 12.0 24.0 Pack Materials-Page 1...
  • Page 64 PACKAGE MATERIALS INFORMATION www.ti.com 2-Apr-2016 *All dimensions are nominal Device Package Type Package Drawing Pins Length (mm) Width (mm) Height (mm) TAS5733LDCAR HTSSOP 2000 367.0 367.0 45.0 Pack Materials-Page 2...
  • Page 68: Important Notice

    IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue.

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