AOpen AP5C User Manual page 57

AMI BIOS
Read Burst Timing*
This parameter adjusts the read wait state between the L2 and the
DRAM cache. Everytime the CPU reads a L2 cache miss, it reads
four continuous addresses from the DRAM cache.
The available settings are X-4-4-4, X-3-3-3 and X-2-2-2. The value of
X depends on the DRAM Lead-off Timing parameter setting. Faster
DRAMs require shorter wait states. The default setting is
Write Burst Timing*
This parameter adjusts the write wait state between the L2 and the
DRAM cache. Each cache write process consists of four continuous
cache cycles and therefore, this function has four numbers to adjust.
The selections are X-4-4-4, X-3-3-3 and X-2-2-2. The value of X
depends on the DRAM Lead-off Timing parameter setting. Faster
DRAMs require shorter wait states. The default setting is
RAS to CAS Delay*
This function allows you to set the wait state between the RAS and
CAS signals. The available settings are 3T and 2T. The default
setting .
3T
*
This parameter appears only if the Chipset Setup Mode parameter in the Advanced
Setup screen is set to Engineer
3-18
.
.
X-4-4-4
.
X-4-4-4
User's Guide