Off-Board Clock I/O - Intel Stratix 10 GX FPGA User Manual

4. Board Components
UG-20046 | 2020.04.02
Source

4.7.2. Off-Board Clock I/O

Table 32.
J3
J4
Table 33.
J2
J1
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Schematic Signal
Name
FPGA_OSC_CLK1
MAXV_OSC_CLK1
CLK_CONFIG
CLK_FPGA_50M
CLK_MAXV_50M
CLK_HILO_P
CLK_HILO_N
U9
CLK_FOGA_B3L_P
CLK_FPGA_B3L_N
PCIE_OB_REFCLK
_P
PCIE_ON_REFCLK
_N
REFCLK_SDI_P
X1
REFCLK_SDI_N
The development board has input and output clocks which can be driven onto the
board. The output clocks can be programmed to different levels and I/O standards
according to the FPGA device's specification.
Off-Board Clock Inputs
Source Schematic Signal
Name
SDI_REFCLK_SMA_P
SDI_REFCLK_SMA_N
Off-Board Clock Outputs
Source Schematic Signal
Names
SMA_CLKOUT_P
SMA_CLKOUT_P
Frequency I/O Standard
LVDS
125 MHz
125 MHz LVDS
125 MHz LVDS
50 MHz 1.8V LVCMOS
50 MHz 1.8V LVCMOS
LVDS
133 MHz
LVDS
LVDS
100 MHz
LVDS
LVDS
100 MHz
LVDS
LVDS
148.5 MHz
LVDS
I/O Standard Intel Stratix 10 FPGA
LVDS T41
LVDS T40
I/O Standard Intel Stratix 10 FPGA
1.8V H23
1.8V G23
®
Intel Stratix
Intel Stratix 10 Application
FPGA Pin Number
BA22 FPGA
configuration
clock
– MAX V clock
– MAX V clock
BH33 FPGA clock
– MAX V clock
M35
HiLo memory
clock
N35
J20
FPGA clock for
Bank 3L
J19
AP41
On board PCIe
reference clock
AP40
P41
SDI reference
clocks
P40
Description
Pin Number
SDI Refclk Input
SDI Refclk Input
Description
Pin Number
SMA clock output
®
10 GX FPGA Development Kit User Guide
47