Texas Instruments TRF7960A Manual page 35

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The IRQ Status register read (0x6C) yields 0x80, which indicates that TX is complete. This is followed by
dummy clock and reset of FIFO with dummy clock. Then, if a tag is in the field and no error is detected by
the reader, a second interrupt is expected and occurs (in this example) approximately 4 ms after first IRQ
is read and cleared.
In the continuation of the example (see
previously recommended, followed by a single read of the FIFO Status register, which indicates that there
are at least 9 bytes to be read out.
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Figure 6-21. IRQ After Inventory Command
Figure 6-22), the IRQ Status register is read using method
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SLOS732G – JUNE 2011 – REVISED MARCH 2020
TRF7960A
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Detailed Description 35