Power; Low-Dropout Voltage Regulators - Motorola W208 Manual

W208 Level 3 Circuit Description
size.
ADD [1:23] – Address Bus for Flash memory/PSRAM.
DATA [0:15] – Data Bus for Flash memory/PSRAM
F1_VCC – This is provided Flash memory I/O voltage.
RnW – Read and Write allows information to be written or read from the memory devices.
nFOE – Flash and PSRAM output enable (Active Low).
FDP – The Flash reset/deep power-down mode control.
nCS3 – This is used as Chip Enable for the Flash Memory.
nCS0 – This is used as Chip Enable for the PSRAM Memory.
nBHE – Enable to address High Byte Information.
nBLE – Enable to address Low Byte Information.
VCCQ – This provides PSRAM memory power supply

13 Power

Low-Dropout Voltage Regulators

13.1
The voltage regulation block consists of seven subblocks.
Several low-dropout (LDO) regulators perform linear voltage regulation. These regulators
supply power to internal analog and digital circuits, to the
processor, and to external memory.
The first LDO (VRPLL
the supply voltages 1.3 V for
The second LDO (VRABB
Triton-Lite analog part.
The third LDO (VRRTC
clock used.
The fourth LDO (VREXTH
generates the supply voltages 2.8 V for supplying an external peripheral to Locosto-Plus
U101.
The fifth LDO (VREXTL
Figure 108: Memory interface
Triton-Lite Pin T12) is a programmable regulator that generates
Locosto-Plus IC
Triton-Lite Pin B2) generates the supply voltage (2.8 V) for the
Triton-Lite Pin N17) is a power rail for embedded 32K real time
Triton-Lite Pin I17) is a programmable regulator that
Triton-Lite Pin G17) generates the supply external peripheral
Service Engineering & Optimization
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Locosto-Plus IC U101 (DSP)
U101.