Processor 3/6 - Intel PC50HS Service Manual

Processor 3/6

5
VCCST
40 PCH_CPU_BCLK_R_DP
R1016 R1017
40 PCH_CPU_BCLK_R_DN
100_04 56.2_1%_04
40 PCH_CPU_PCIBCLK_R_DP
CPU CPU
NEAR CPU
40 PCH_CPU_PCIBCLK_R_DN
CPU R1019 0_04
61 H_CPU_SVIDDAT
CPU R1021 0_04
61 H_CPU_SVIDCLK
CPU R1020 0_04
61 H_CPU_SVIDALRT#
H_PROCHOT#
CPU R1022 499_1%_04
61,72 H_PROCHOT#
D CPU R1023 0_04
40 CLKOUT_CPURTC
36 PCH_THERMTRIP#
37 H_PM_SYNC
CPU R1027 20_1%_04
37 H_PM_DOWN
CPU R1029 0_04
37 PLTRST_CPU#
CPU R1030 0_04
37,49 H_PECI
40 H_PWRGD
CPU R1031 *1K_04
40 H_TRST#
39 H_TMS
PDG P.474
39 H_TDO
39 H_TDI
39 H_TCK
CPU
CLOSE TO CPU 150_1%_04
40 CPU_24MHZ_R_DP
40 CPU_24MHZ_R_DN
C
Each of the DPIP port are DisplayPort* Receiver port
that direct display stream to a Type-C thru TCP ports.
U72D
BL38
47 TCP0_TX1_DP
TCP0_TX_P1
BL37
47 TCP0_TX1_DN TCP0_TX_N1
BP37
47 TCP0_TX0_DP
TCP0_TX_P0
BP38
TCP_0 47 TCP0_TX0_DN
TCP0_TX_N0
BK40
47 TCP0_TXRX1_DP
TBT TCP0_TXRX_P1
BK41
47 TCP0_TXRX1_DN
TCP0_TXRX_N1
BL41
47 TCP0_TXRX0_DP TCP0_TXRX_P0
BL40
47 TCP0_TXRX0_DN
TCP0_TXRX_N0
DIFF=85ohm
BN37
47 TCP0_AUX_DP
TCP0_AUX_P
BN38
47 TCP0_AUX_DN TCP0_AUX
BD40
RSVD_TP_1
BD41
RSVD_TP_2
BD37
RSVD_TP_3
CLOSE TO CPU
BD36
RSVD_TP_4
CPU R1047 2.2K_1%_04 BP41
TCP0_MBIAS_RCOMP
BP40
RSVD_TP_5
BG38
TCP1_TX_P1
BG37
TCP1_TX_N1
BJ37
TCP1_TX_P0
BJ38
TCP1_TX_N0
BG40
TCP_1
TCP1_TXRX_P1
B BG41
TCP1_TXRX_N1
BH41
TCP1_TXRX_P0
BH40
TCP1_TXRX_N0
BH37
TCP1_AUX_P
BH38
TCP1_AUX
BW37
TCP2_TX_P1
BW38
TCP2_TX_N1
BT38
TCP2_TX_P0
BT37
TCP2_TX_N0
TCP_2
BW41
TCP2_TXRX_P1
BW40
TCP2_TXRX_N1
BU40
TCP2_TXRX_P0
BU41
TCP2_TXRX_N0
BU38
TCP2_AUX_P
BU37
TCP2_AUX
CD37
TCP3_TX_P1
CD38
TCP3_TX_N1
CB38
TCP3_TX_P0
CB37
TCP3_TX_N0
TCP_3 CC41
TCP3_TXRX_P1
CC40
TCP3_TXRX_N1
CB40
TCP3_TXRX_P0
CB41
TCP3_TXRX_N0
CC38
TCP3_AUX_P
CC37
TCP3_AUX
D34
RSVD_TP_45
A CPU
T108 E34
DISP_UTILS
PROC_AUDIO_SDO
A32
AUDOUT
A31
39 AUD_AZACPU_SDO_R
AUDIN
B32
39 AUD_AZACPU_SCLK
AUDCLK
CPU_EAR
F36
EAR
TGL_H_CPU_IP_EXT
PROC_AUDIO_SDO
CPU R1058 20_1%_04
39 AUD_AZACPU_SDI
CLOSE TO CPU
5
4 3
U72E
5 OF 15 CPU_ID
C36 CT3
BCLK_P RSVD_18
D36
BCLK
CPU_CFG15
J40
CFG_15 CFG14_PCIE4_LANE
C37 L41 R1018
PCI_BCLK_P CFG_14
CPU_CFG13
B37 J41
PCI_BCLK CFG_13 CPU_CFG12
N41
CFG_12
VIDSOUT CPU_CFG11
D32 L40
VIDSOUT CFG_11
CPU_CFG10
VIDSCK E32 N40
VIDSCK CFG_10
VIDALERT# CPU_CFG9
F32 M39
VIDALERT# CFG_9
PROCHOT# CPU_CFG8
H35 J37
PROCHOT# CFG_8 CPU_CFG7
M38
CFG_7
CLKOUT_CPURTC_R CFG6_PEG_BI R1024
CR22 J38
RTC_CLK CFG_6
CFG5_PEG_BI
J35 R1025
CFG_5
CFG4_eDP_EN R1026
F34 N39
THERMTRIP# CFG_4
CPU_CFG3
CR23 L37
PM_SYNC CFG_3
PM_DOWN CFG2_PEG_LANE R1028
CR24 M35
PM_DOWN CFG_2
PLTRST_CPU#_R CPU_CFG1
CR25 M37
DRAM_RESET# CFG_1 CPU_CFG0
PECI CP25 N36
PECI CFG_0
CT25
PROCPWRGD CPU_CFG17
M41
CFG_17
H_CATERR# CPU_CFG16
H36 L39
CATERR# CFG_16
H_PREQ#
H39 H34
BPM#_3 PROC_PREQ# H_PREQ#
H_PRDY#
H40 G36
H_PRDY#
BPM#_2 PROC_PRDY#
G38
BPM#_1
CFG_RCOMP CPU R1032
H37 A34
BPM#_0 CFG_RCOMP
H_TRST# VCCSTPWRGOOD_TCSS CPU R1033
E40 CP23
PROC_TRST# VCCSTPWRGOOD_TCSS
H_TMS VCCST_PWRGD
G41 CP24 CPU R1034
PROC_TMS VCCST_PWRGD
H_TDO
G39
PROC_TDO
H_TDI
F39 CR3
PROC_TDI SKTOCC#
H_TCK G40 CU23 C10_WAKE CPU R1035
PROC_TCK CPU_WAKE
F37
RSVD_1
E37 VCCSTPWRGOOD_TCSS
RSVD_2 CPU
R1037 TC_RCOMP_P
BR41
TC_RCOMP_P
TC_RCOMP_N
BR40
TC_RCOMP
C39
CLK_XTAL_P
D39
CPU_CFG17
CLK_XTAL
CPU_CFG16
CPU_CFG15
TGL_H_CPU_IP_EXT
CPU_CFG13
CPU_CFG12
CPU_CFG11
CPU_CFG10
CPU_CFG9
CPU_CFG8
4 OF 15
AC40
CPU_CFG7
DPIP3_RXP_3
AC41 CPU_CFG3
DPIP3_RXN_3
AD39 CPU_CFG1
DPIP3_RXP_2
AD40
CPU_CFG0
DPIP3_RXN_2
AC37
DPIP3_RXP_1
AC38
DPIP3_RXN_1
AD36 DPIP_3
DPIP3_RXP_0
AD37
DPIP3_RXN_0
AN38
48 PROCHOT_PD
DPIP3_AUX_P
AN39
DPIP3_AUX
AE40
DPIP2_RXP_3
AE41
DPIP2_RXN_3 39 VRALERT#_PD
AF39
DPIP2_RXP_2
3.3VA
AF40
DPIP2_RXN_2
AF36
DPIP2_RXP_1
AF37
DPIP2_RXN_1
AG37 DPIP_2
DPIP2_RXP_0
AG38
DPIP2_RXN_0
AR39
DPIP2_AUX_P
AR40
DPIP2_AUX
AG40
DPIP1_RXP_3 49,72 AC_IN#
AG41
DPIP1_RXN_3
AJ39
DPIP1_RXP_2
AJ40
DPIP1_RXN_2
AJ36
49 H_PROCHOT_EC
DPIP1_RXP_1
AJ37
DPIP1_RXN_1
AK37 DPIP_1
DPIP1_RXP_0
AK38
DPIP1_RXN_0
AR36
DPIP1_AUX_P
AR37
DPIP1_AUX
C1594 0.1u_10V_X5R_04 CPU
AL36
DPIP0_RXP_3 DP_A3 27
AL37 C1595 0.1u_10V_X5R_04 CPU
DP_A#3 27
DPIP0_RXN_3
C1596 0.1u_10V_X5R_04 CPU
AK40
DPIP0_RXP_2 DP_A2 27
AK41 C1597 0.1u_10V_X5R_04 CPU
DP_A#2 27
DPIP0_RXN_2
AL39 C1598 0.1u_10V_X5R_04 CPU
DPIP0_RXP_1 DP_A1 27
C1599 0.1u_10V_X5R_04 CPU
AL40
DP_A#1 27
DPIP0_RXN_1
AM37 C1600 0.1u_10V_X5R_04 CPU
DPIP0_RXP_0 DP_A0 27
C1601 0.1u_10V_X5R_04 CPU
AM38
DPIP0_RXN_0 DP_A#0 27
C1602 0.1u_10V_X5R_04 CPU
AT37
DPIP0_AUX_P DP_A_AUX 27
AT38 C1603 0.1u_10V_X5R_04 CPU
DP_A_AUX# 27
DPIP0_AUX
AM41
DPIP_0
RSVD_TP_6
AM40
RSVD_TP_7
AN41
RSVD_TP_8
AC35
DPIP3_HPD 0311 add
10,43,49,61 ALL_SYS_PWRGD
AE37
DPIP2_HPD
AE35
DPIP1_HPD CPU
R1511 0_04
AE38
CPU_DPIP0_HPD_S 27
DPIP0_HPD
CPU R1054 150_1%_04
AT41
DPIP3_RCOMP
AU40 CPU R1055 150_1%_04
DPIP2_RCOMP
CPU R1056 150_1%_04
AU39
DPIP1_RCOMP
AT40 CPU R1057 150_1%_04
DPIP0_RCOMP
CLOSE TO CPU
4 3
2 1
PCI Express* Static x16 Lanes Numbering Reversal
1: Normal (DEFAULT)
CFG2
<==
0: Reversed
*1K_04 CPU
eDP enable
CFG4 1: Disable
0: Enable
<==
*1K_04 CPU
*1K_04 CPU PCIE Express* Bifurcation
1K_04 CPU
1K_04 CPU 11: 1x16 PCI Express* (DEFAULT)
CFG[6:5]
10: 2x8 PCI Express*
01: Reserved
00: 1x8,2x4 PCI Express*
37
CLOSE TO CPU PEG60 (PCIE4) Lane Reversal
37
49.9_1%_04
CFG14 1: Normal (DEFAULT) <==
*0_04 VCCST_PWRGD
0: Reversed
H_VCCST_PWRGD
60.4_1%_04
H_SKTOCC_N 38
0_04
CPU_C10_WAKE 40
R1040 0_04
VCCST_OVERRIDE 41,43 CPU_EAR
CPU R1036 1K_04
CPU R1038 *1K_04
H_TCK CPU R1039 51_04
VCCIO_OUT
VCCST_PWRGD
CPU C1354 *0.1u_10V_X7R_04
R1482 1K_04 CPU
R1483 1K_04 CPU
R1484 1K_04 CPU
R1485 1K_04 CPU
R1486 1K_04 CPU
R1487 1K_04 CPU
R1488 1K_04 CPU
H_CATERR#
CPU R1041 1K_04
R1489 1K_04 CPU
R1490 1K_04 CPU
H_TDO
CPU R1042 51_04
R1491 1K_04 CPU
R1492 1K_04 CPU
R1493 1K_04 CPU
R1494 1K_04 CPU
CPU_ID
CPU R1043 *10K_04
0305 knight check PDG
CPU R1044 *0_04
RB751S-40H D48
CPU R1045 0_04 C A H_PROCHOT# R1046 1K_04
CPU
D
CPU R1048 100K_04 C1355
2
G
S Q64A *47p_50V_NPO_04
CPU R1049 200K_04 SM2004KDWH CPU
CPU
C A
D49 RB751S-40H D
5 G
S Q64B
SM2004KDWH CAD Note: Capacitor need to be placed
CPU close to buffer output pin
VCCST_PWRGD VCCST
VDD3
R1050
1K_04
CPU
H_VCCST_PWRGD
R1051 Q65A
SM2004KDWH
100K_04
CPU D
CPU
R1053
SYS_PWRGD# 2 D50
G
*RB751S-40H *100_04
S
CPU
R1052 D A C
SUSB#
0_04
CPU
5 G
A C
S Q65B
SM2004KDWH
CPU D51
*RB751S-40H
C1356
*0.1u_10V_X7R_04
37,43 PM_PCH_PWROK
CPU
Title Title Title [04] CPU 3/6-TCP/CLK/DPIN/SIDE [04] CPU 3/6-TCP/CLK/DPIN/SIDE [04] CPU 3/6-TCP/CLK/DPIN/SIDE
Size Size Size Document Number Document Number Document Number
6-71-PC5H0-D02 6-71-PC5H0-D02 6-71-PC5H0-D02
Custom Custom Custom PC50HS-D02 PC50HS-D02 PC50HS-D02
Date: Date: Date: Friday, May 14, 2021 Friday, May 14, 2021 Friday, May 14, 2021 Sheet Sheet Sheet 4 4 4
2 1
Schematic Diagrams
D
<==
VCCSTG
Sheet 4 of 79
C
VCCST
Processor 3/6
3.3VA
VCCSTG
B
10,37,43,57,58,63
A
Rev Rev Rev
D02 D02 D02
of of of 79 79 79
Processor 3/6 B - 5