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IC
EMIF A
TIMER 2
TIMER 1
TIMER 0
VCXO
INTERPOLATED
CONTROL
PORT (VIC)
VIDEO PORT 2
(VP2)
VIDEO PORT 0
(VP0)
OR
8/10-BIT VP0
AND
McBSP0
OR
McASP0
CONTROL
VIDEO PORT 1
(VP1)
OR
8/10-BIT VP1
AND
McBSP1
OR
McASP0
DATA
PCI-66
OR
HPI32
OR
HPI16
AND
EMAC
MDIO
6-14
L1P CACHE
DIRECT MAPPED
16K-BYTE TOTAL
C64 x DSP CORE
INSTRUCTION FETCH
CONTROL
REGISTERS
INSTRUCTION DISPATCH
CONTROL
ADVANCED INSTRUCTION PACKET
LOGIC
INSTRUCTION DECODE
DATA PATH A
DATA PATH B
TEST
A REGISTER FILE
B REGISTER FILE
A31 - A16
B31 - B16
ADVANCED
A15 - A0
B15 - B0
IN-CIRCUIT
EMULATION
INTERRUPT
.L1
.S1
.M1
.D1
.D2
.M2
.S2
.L2
CONTROL
L1D CACHE
2-WAY SET-ASSOCIATIVE
16K-BYTE TOTAL
PLL
BOOT
(x 1, x 6, x 12)
CONFIGURATION
POWER-DOWN
LOGIC
GP0
I2C0
PCS-G70N/G70NP/G70NP2
PCS-G70S/G70SP
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