Table of Contents
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TI-DSP-ENC(2/5)
IC201
(2/5)
TMS320DM642GDK6E3
R310
EMIFA
22
162
003
TENC_EMIFA_xACE0
ACE0[K25]
249
CL301 1.0
ACE1[K24]
328
CL302 1.0
ACE2[K23]
66
CL303 1.0
ACE3[L26]
003
TENC_EMIFA_xABE(7..0)
RB302 1
2
248
TENC_EMIFA_xABE0
ABE0[L24]
22
TENC_EMIFA_xABE1
3
4
327
ABE1[L23]
65
TENC_EMIFA_xABE2
5
6
ABE2[M26]
7
8
160
TENC_EMIFA_xABE3
ABE3[M25]
RB303 1
2
62
TENC_EMIFA_xABE4
ABE4[R26]
22
157
TENC_EMIFA_xABE5
3
4
ABE5[R25]
5
6
322
TENC_EMIFA_xABE6
ABE6[T23]
7
8
393
TENC_EMIFA_xABE7
ABE7[T22]
396
CL304 1.0
AHOLDA[N22]
240
CL305 1.0
AHOLD[W24]
395
D2S_3.3V
CL306 1.0
ABUSREQ[P22]
164
002
TENC_EMIFA_AECLKIN
AECLKIN[H25]
329
CL307 1.0
AECLKOUT2[J23]
JC305
0
68
003
TENC_EMIFA_AECLKOUT1
AECLKOUT1[J26]
RB301 1
2
161
003
TENC_EMIFA_ASDCKE
ASDCKE[L25]
22
3
4
163
003
TENC_EMIFA_xASDCAS
AARE/ASDCAS/ASADS/ASRE[J25]
250
5
6
003
TENC_EMIFA_xASDRAS
AAOE/ASDRAS/ASOE[J24]
7
8
67
003
TENC_EMIFA_xASDWE
AAWE/ASDWE/ASWE[K26]
398
AARDY[L22]
394
R308
CL308 1.0
10k
ASOE3[R22]
397
NM
CL309 1.0
APDT[M22]
003
TENC_EMIFA_AEA(16..3)
RB304
7
8
247
TENC_EMIFA_AEA3
AEA3[M24]
22
5
6
326
TENC_EMIFA_AEA4
AEA4[M23]
3
4
64
TENC_EMIFA_AEA5
AEA5[N26]
1
2
246
TENC_EMIFA_AEA6
AEA6[N24]
RB305 1
2
325
TENC_EMIFA_AEA7
AEA7[N23]
22
3
4
63
TENC_EMIFA_AEA8
AEA8[P26]
245
TENC_EMIFA_AEA9
5
6
AEA9[P24]
324
TENC_EMIFA_AEA10
7
8
AEA10[P23]
RB306
7
8
244
TENC_EMIFA_AEA11
AEA11[R24]
22
323
TENC_EMIFA_AEA12
5
6
AEA12[R23]
3
4
156
TENC_EMIFA_AEA13
AEA13[T25]
1
2
243
TENC_EMIFA_AEA14
AEA14[T24]
TENC_EMIFA_AEA15
R311
22
60
AEA15[U26]
R312
22
155
TENC_EMIFA_AEA16
AEA16[U25]
242
CL310 1.0
AEA17[U24]
320
CL311 1.0
AEA18[V23]
59
AEA19[V26]
154
AEA20[V25]
241
AEA21[V24]
321
AEA22[U23]
D2S_3.3V
D_GND
003
TENC_EMIFA_AEA(16..3)
D2S_3.3V
C301
0.1uF
AEA[22:21]:Boot mode
D_GND
00 - No boot
01 - HPI boot
10 - Reserved
11 - EMIFA boot
TENC_EMIFA_AEA16
TENC_EMIFA_AEA15
AEA[20:19]:Clock mode select for EMIFA (AECLKIN_SEL[1:0])
TENC_EMIFA_AEA14
00 - AECLKIN (default mode)
TENC_EMIFA_AEA13
01 - CPU/4 Clock Rate
TENC_EMIFA_AEA12
10 - CPU/6 Clock Rate
TENC_EMIFA_AEA11
11 - Reserved
TENC_EMIFA_AEA10
TENC_EMIFA_AEA9
TENC_EMIFA_AEA8
TENC_EMIFA_AEA7
TENC_EMIFA_AEA6
TENC_EMIFA_AEA5
TENC_EMIFA_AEA4
TENC_EMIFA_AEA3
003
TENC_EMIFA_xASDWE
TENC_EMIFA_xABE1
003
TENC_EMIFA_xASDCAS
TENC_EMIFA_xABE0
003
TENC_EMIFA_xASDRAS
JC306
003
TENC_EMIFA_ASDCKE
003
TENC_EMIFA_AECLKOUT1
003
TENC_EMIFA_xACE0
003
TENC_EMIFA_xABE(7..0)
003
TENC_EMIFA_AED(63..0)
PCS-G70N/G70NP/G70NP2
PCS-G70S/G70SP
A
B
TENC_EMIFA_AED(63..0) 003
@NS
171
7
8
RB307
TENC_EMIFA_AED0
AED0[B24]
10
78
5
6
TENC_EMIFA_AED1
AED1[A24]
172
3
4
TENC_EMIFA_AED2
VFPTENC_V1_YUV0
AED2[B23]
173
1
2
TENC_EMIFA_AED3
VFPTENC_V1_YUV1
AED3[B22]
258
7
8
RB308
TENC_EMIFA_AED4
VFPTENC_V1_YUV2
AED4[C22]
10
79
5
6
TENC_EMIFA_AED5
VFPTENC_V1_YUV3
AED5[A23]
259
3
4
TENC_EMIFA_AED6
VFPTENC_V1_YUV4
AED6[C21]
174
1
2
TENC_EMIFA_AED7
VFPTENC_V1_YUV5
AED7[B21]
336
RB309
7
8
TENC_EMIFA_AED8
VFPTENC_V1_YUV6
AED8[D21]
10
81
5
6
TENC_EMIFA_AED9
VFPTENC_V1_YUV7
AED9[A21]
260
3
4
TENC_EMIFA_AED10
AED10[C20]
013
VFPTENC_V1_YUV(7..0)
175
1
2
TENC_EMIFA_AED11
AED11[B20]
337
7
8
RB310
TENC_EMIFA_AED12
AED12[D20]
10
82
5
6
TENC_EMIFA_AED13
AED13[A20]
338
3
4
TENC_EMIFA_AED14
AED14[D19]
261
1
2
TENC_EMIFA_AED15
AED15[C19]
251
7
8
RB311
TENC_EMIFA_AED16
AED16[H24]
10
330
5
6
TENC_EMIFA_AED17
AED17[H23]
70
3
4
TENC_EMIFA_AED18
AED18[G26]
331
1
2
TENC_EMIFA_AED19
AED19[G23]
165
7
8
RB312
TENC_EMIFA_AED20
AED20[G25]
10
252
5
6
TENC_EMIFA_AED21
AED21[G24]
001,003
27M_TENC
71
3
4
TENC_EMIFA_AED22
AED22[F26]
332
1
2
TENC_EMIFA_AED23
AED23[F23]
001,003
VSS_HSYNC
166
RB313
7
8
TENC_EMIFA_AED24
AED24[F25]
001,003
VSS_VSYNC
10
253
5
6
TENC_EMIFA_AED25
AED25[F24]
001,003
VSS_FIELD
167
3
4
TENC_EMIFA_AED26
AED26[E25]
254
1
2
TENC_EMIFA_AED27
AED27[E24]
168
7
8
RB314
TENC_EMIFA_AED28
AED28[D25]
013
VFPTENC_V2_YUV(7..0)
10
73
5
6
TENC_EMIFA_AED29
AED29[D26]
169
3
4
TENC_EMIFA_AED30
VFPTENC_V2_YUV0
AED30[C25]
74
1
2
TENC_EMIFA_AED31
VFPTENC_V2_YUV1
AED31[C26]
53
7
8
RB315
TENC_EMIFA_AED32
VFPTENC_V2_YUV2
AED32[AD26]
10
148
5
6
TENC_EMIFA_AED33
VFPTENC_V2_YUV3
AED33[AD25]
149
3
4
TENC_EMIFA_AED34
VFPTENC_V2_YUV4
AED34[AC25]
54
1
2
TENC_EMIFA_AED35
VFPTENC_V2_YUV5
AED35[AC26]
237
RB316
7
8
TENC_EMIFA_AED36
VFPTENC_V2_YUV6
AED36[AB24]
10
150
5
6
TENC_EMIFA_AED37
VFPTENC_V2_YUV7
AED37[AB25]
316
3
4
TENC_EMIFA_AED38
AED38[AB23]
238
1
2
TENC_EMIFA_AED39
AED39[AA24]
151
7
8
RB317
TENC_EMIFA_AED40
AED40[AA25]
10
317
5
6
TENC_EMIFA_AED41
AED41[AA23]
56
3
4
TENC_EMIFA_AED42
AED42[AA26]
239
1
2
TENC_EMIFA_AED43
AED43[Y24]
152
7
8
RB318
TENC_EMIFA_AED44
AED44[Y25]
10
318
5
6
TENC_EMIFA_AED45
AED45[Y23]
57
3
4
TENC_EMIFA_AED46
AED46[Y26]
319
1
2
TENC_EMIFA_AED47
AED47[W23]
230
7
8
RB319
TENC_EMIFA_AED48
AED48[AD19]
10
311
5
6
TENC_EMIFA_AED49
AED49[AC19]
001,003
27M_TENC
45
3
4
TENC_EMIFA_AED50
AED50[AF20]
312
1
2
TENC_EMIFA_AED51
AED51[AC20]
001,003
VSS_HSYNC
142
RB320
7
8
TENC_EMIFA_AED52
AED52[AE20]
001,003
VSS_VSYNC
10
231
5
6
TENC_EMIFA_AED53
AED53[AD20]
001,003
VSS_FIELD
46
3
4
TENC_EMIFA_AED54
AED54[AF21]
313
1
2
TENC_EMIFA_AED55
AED55[AC21]
143
7
8
RB321
TENC_EMIFA_AED56
AED56[AE21]
10
232
5
6
TENC_EMIFA_AED57
AED57[AD21]
144
3
4
TENC_EMIFA_AED58
AED58[AE22]
233
1
2
TENC_EMIFA_AED59
AED59[AD22]
234
7
8
RB322
TENC_EMIFA_AED60
AED60[AD23]
10
145
5
6
TENC_EMIFA_AED61
AED61[AE23]
48
3
4
TENC_EMIFA_AED62
AED62[AF23]
49
1
2
TENC_EMIFA_AED63
AED63[AF24]
FB301
8M*16bit,16MB
D_GND
21
53
1
2
21
TENC_EMIFA_AED15
TENC_EMIFA_AEA16
BA1
DQ15
BA1
RB323
20
51
3
4
20
TENC_EMIFA_AED14
22
TENC_EMIFA_AEA15
BA0
DQ14
BA0
35
50
35
5
6
TENC_EMIFA_AED13
TENC_EMIFA_AEA14
A11
DQ13
A11
22
48
7
8
22
TENC_EMIFA_AED12
TENC_EMIFA_AEA13
A10
DQ12
A10
34
47
1
2
34
TENC_EMIFA_AED11
TENC_EMIFA_AEA12
A9
DQ11
RB324
A9
33
45
33
3
4
TENC_EMIFA_AED10
22
TENC_EMIFA_AEA11
A8
DQ10
A8
32
44
32
5
6
TENC_EMIFA_AED9
TENC_EMIFA_AEA10
A7
DQ9
A7
31
42
7
8
31
TENC_EMIFA_AED8
TENC_EMIFA_AEA9
A6
DQ8
A6
30
13
30
1
2
TENC_EMIFA_AED7
TENC_EMIFA_AEA8
A5
DQ7
RB325
A5
29
11
29
3
4
TENC_EMIFA_AED6
22
TENC_EMIFA_AEA7
A4
DQ6
A4
26
10
5
6
26
TENC_EMIFA_AED5
TENC_EMIFA_AEA6
A3
DQ5
A3
25
8
7
8
TENC_EMIFA_AED4
TENC_EMIFA_AEA5
25
A2
DQ4
A2
24
7
24
1
2
TENC_EMIFA_AED3
TENC_EMIFA_AEA4
A1
DQ3
RB326
A1
23
5
3
4
23
TENC_EMIFA_AED2
22
TENC_EMIFA_AEA3
A0
DQ2
A0
4
5
6
TENC_EMIFA_AED1
DQ1
19
2
19
7
8
TENC_EMIFA_AED0
CS
DQ0
CS
16
16
WE
WE
17
17
CAS
CAS
18
18
RAS
RAS
39
39
TENC_EMIFA_xABE3
DQMH
DQMH
15
TENC_EMIFA_xABE2
15
DQML
DQML
37
36
37
CKE
NC1
CKE
0
38
40
JC307
0
38
CLK
NC2
CLK
IC301
MT48LC8M16A2P-75-Y15WTR
D_GND
D_GND
C
DSP-113 (3/20)
DSP-113 (3/20)
TI-DSP-ENC(3/5)
IC201
(3/5)
TMS320DM642GDK6E3
272
43
VP0D_0[AF18]
VP2D_0[C8]
140
349
VP2D_1[D8]
VP0D_1[AE18]
42
93
R326
22
VP0D_2/CLKX0[AF17]
VP2D_2[A9]
41
186
R327
22
VP0D_3/FSX0[AF16]
VP2D_3[B9]
138
271
R328
22
VP0D_4/DX0[AE16]
VP2D_4[C9]
227
348
R329
22
VP0D_5/CLKS0[AD16]
VP2D_5[D9]
308
92
R330
22
VP0D_6/DR0[AC16]
VP2D_6[A10]
381
185
R331
22
VP0D_7/FSR0[AB16]
VP2D_7[B10]
137
270
R332
22
VP0D_8/CLKR0[AE15]
VP2D_8[C10]
226
347
R333
22
VP0D_9[AD15]
VP2D_9[D10]
307
91
VP2D_10[A11]
VP0D_10[AC15]
380
184
VP0D_11[AB15]
VP2D_11[B11]
225
269
VP0D_12/ACLKR0[AD14]
VP2D_12[C11]
306
346
VP0D_13/AFSR0[AC14]
VP2D_13[D11]
379
415
VP0D_14/AHCLKR0[AB14]
VP2D_14[E11]
224
183
VP0D_15/AMUTEIN0[AD13]
VP2D_15[B12]
305
268
VP0D_16/AMUTE0[AC13]
VP2D_16[C12]
378
345
VP2D_17[D12]
VP0D_17/ACLKX0[AB13]
223
414
VP0D_18/AFSX0[AD12]
VP2D_18[E12]
413
304
VP0D_19/AHCLKX0[AC12]
VP2D_19[E13]
JC309
0
39
95
JC311
0
VP0CLK0[AF14]
VP2CLK0[A7]
37
89
CL312 1.0
VP0CLK1[AF12]
VP2CLK1[A13]
CL315 1.0
R313
47
139
187
R334
47
VP0CTL0[AE17]
VP2CTL0[B8]
R314
47
309
350
R335
47
VP0CTL1[AC17]
VP2CTL1[D7]
R315
47
273
R336
47
228
VP0CTL2[AD17]
VP2CTL2[C7]
JC313
30
287
VP1D_0[AF5]
RESET[P4]
31
191
CL314 1.0
VP1D_1[AF6]
NMI[B4]
128
VP1D_2/CLKX1[AE6]
217
VP1D_3/FSX1[AD6]
298
122
VP1D_4/DX1[AC6]
CLKIN[AC2]
129
VP1D_5/CLKS1[AE7]
218
VP1D_6/DR1[AD7]
299
120
VP1D_7/FSR1[AC7]
CLKMODE0[AA2]
219
126
VP1D_8/CLKR1[AD8]
CLKMODE1[AE4]
300
433
VP1D_9[AC8]
PLLV[V6]
131
VP1D_10[AE9]
220
VP1D_11[AD9]
301
411
R319
10
VP1D_12/AXR0_0[AC9]
TMS[E15]
221
177
R320
10
VP1D_13/AXR0_1[AD10]
TDO[B18]
302
84
R321
10
VP1D_14/AXR0_2[AC10]
TDI[A18]
133
86
R322
10
VP1D_15/AXR0_3[AE11]
TCK[A16]
222
343
R323
10
VP1D_16/AXR0_4[AD11]
TRST[D14]
303
87
R324
10
VP1D_17/AXR0_5[AC11]
EMU0[A15]
376
266
R325
10
VP1D_18/AXR0_6[AB11]
EMU1[C14]
377
180
VP1D_19/AXR0_7[AB12]
EMU2[B15]
265
EMU3[C15]
JC310
0
33
342
VP1CLK0[AF8]
EMU4[D15]
35
179
CL313 1.0
VP1CLK1[AF10]
EMU5[B16]
R316
47
29
264
VP1CTL0[AF4]
EMU6[C16]
R317
47
127
85
VP1CTL1[AE5]
EMU7[A17]
R318
47
216
341
VP1CTL2[AD5]
EMU8[D16]
178
EMU9[B17]
263
EMU10[C17]
340
EMU11[D17]
McBSP
275
CLOCK
TOUT0/MAC_EN[C5]
98
RESET
TINP0[A4]
190
JTAG
TOUT1/LENDIAN[B5]
97
TIMER
TINP1[A5]
8M*16bit,16MB
8M*16bit,16MB
D_GND
53
1
2
21
53
1
2
TENC_EMIFA_AED31
TENC_EMIFA_AEA16
TENC_EMIFA_AED47
DQ15
BA1
DQ15
RB327
51
3
4
20
51
3
4
TENC_EMIFA_AED30
TENC_EMIFA_AEA15
TENC_EMIFA_AED46
DQ14
22
BA0
DQ14
50
35
50
5
6
TENC_EMIFA_AED29
TENC_EMIFA_AEA14
5
6
TENC_EMIFA_AED45
DQ13
A11
DQ13
48
7
8
22
48
7
8
TENC_EMIFA_AED28
TENC_EMIFA_AEA13
TENC_EMIFA_AED44
DQ12
A10
DQ12
47
1
2
34
47
1
2
TENC_EMIFA_AED27
TENC_EMIFA_AEA12
TENC_EMIFA_AED43
DQ11
A9
DQ11
45
RB328
33
45
3
4
TENC_EMIFA_AED26
TENC_EMIFA_AEA11
3
4
TENC_EMIFA_AED42
DQ10
22
A8
DQ10
44
32
44
5
6
TENC_EMIFA_AED25
TENC_EMIFA_AEA10
5
6
TENC_EMIFA_AED41
DQ9
A7
DQ9
42
7
8
31
42
7
8
TENC_EMIFA_AED24
TENC_EMIFA_AEA9
TENC_EMIFA_AED40
DQ8
A6
DQ8
13
30
13
1
2
TENC_EMIFA_AED23
TENC_EMIFA_AEA8
1
2
TENC_EMIFA_AED39
DQ7
A5
DQ7
RB329
11
29
11
3
4
TENC_EMIFA_AED22
TENC_EMIFA_AEA7
3
4
TENC_EMIFA_AED38
DQ6
22
A4
DQ6
10
5
6
26
10
5
6
TENC_EMIFA_AED21
TENC_EMIFA_AEA6
TENC_EMIFA_AED37
DQ5
A3
DQ5
8
7
8
TENC_EMIFA_AED20
TENC_EMIFA_AEA5
25
8
7
8
TENC_EMIFA_AED36
DQ4
A2
DQ4
7
24
7
1
2
TENC_EMIFA_AED19
TENC_EMIFA_AEA4
1
2
TENC_EMIFA_AED35
DQ3
A1
DQ3
RB330
5
3
4
23
5
3
4
TENC_EMIFA_AED18
TENC_EMIFA_AEA3
TENC_EMIFA_AED34
DQ2
22
A0
DQ2
4
5
6
TENC_EMIFA_AED17
4
5
6
TENC_EMIFA_AED33
DQ1
DQ1
2
19
2
7
8
TENC_EMIFA_AED16
7
8
TENC_EMIFA_AED32
DQ0
CS
DQ0
16
WE
17
CAS
18
RAS
39
TENC_EMIFA_xABE5
DQMH
TENC_EMIFA_xABE4
15
DQML
36
37
36
NC1
CKE
NC1
40
JC308
0
38
40
NC2
CLK
NC2
IC302
IC303
MT48LC8M16A2P-75-Y15WTR
MT48LC8M16A2P-75-Y15WTR
D_GND
7-35
7-35
D
E
VFPAFP_YUV(7..0)
001,013
VFPAFP_YUV0
VFPAFP_YUV1
VFPAFP_YUV2
VFPAFP_YUV3
VFPAFP_YUV4
VFPAFP_YUV5
VFPAFP_YUV6
VFPAFP_YUV7
27M_TENC
001,003
VSS_HSYNC
001,003
D2S_3.3V
VSS_VSYNC
001,003
C332
VSS_FIELD
001,003
FB302
0.1uF
NM
NM
0
xTENC_RST
001,002
R341
X301
22
50MHz
4
D_GND
NM
NM
Vdd
C323
JC314
0
NM
3
1
0.001uF
OUT
CONT
D_GND
Vss
JC315
0
2
TENC CLKIN
TENC_CLK
002
D_GND
D2S_3.3V
FL301
1
EMI
2
CNTI2F_JT_TMS
004,006,009
IN
OUT
GND
TENCTDEC_JT_DATA
006
C333
C331
3
10uF
0.1uF
CNTENC_JT_DATA
004
16V
CNTI2F_JT_TCK
004,006,009
CNTI2F_JT_TRST
004,006,009
D_GND
TI2FCN_JT_EMU0
004,006,009
TI2FCN_JT_EMU1
004,006,009
D2S_3.3V
R340
1k
MAC_EN
R339
1k NM
R338
1k NM
Endian
R337
1k
D_GND
8M*16bit,16MB
D_GND
D_GND
21
53
1
2
TENC_EMIFA_AEA16
TENC_EMIFA_AED63
BA1
DQ15
RB335
RB331
20
51
3
4
TENC_EMIFA_AEA15
TENC_EMIFA_AED62
22
22
BA0
DQ14
35
50
TENC_EMIFA_AEA14
5
6
TENC_EMIFA_AED61
A11
DQ13
22
48
7
8
TENC_EMIFA_AEA13
TENC_EMIFA_AED60
A10
DQ12
34
47
1
2
TENC_EMIFA_AEA12
TENC_EMIFA_AED59
A9
DQ11
RB332
RB336
33
45
TENC_EMIFA_AEA11
3
4
TENC_EMIFA_AED58
22
22
A8
DQ10
32
44
TENC_EMIFA_AEA10
5
6
TENC_EMIFA_AED57
A7
DQ9
31
42
7
8
TENC_EMIFA_AEA9
TENC_EMIFA_AED56
A6
DQ8
30
13
TENC_EMIFA_AEA8
1
2
TENC_EMIFA_AED55
RB337
A5
DQ7
RB333
29
11
TENC_EMIFA_AEA7
3
4
TENC_EMIFA_AED54
22
22
A4
DQ6
26
10
5
6
TENC_EMIFA_AEA6
TENC_EMIFA_AED53
A3
DQ5
TENC_EMIFA_AEA5
25
8
7
8
TENC_EMIFA_AED52
A2
DQ4
24
7
TENC_EMIFA_AEA4
1
2
TENC_EMIFA_AED51
RB334
A1
DQ3
RB338
23
5
3
4
TENC_EMIFA_AEA3
TENC_EMIFA_AED50
22
22
A0
DQ2
4
5
6
TENC_EMIFA_AED49
DQ1
19
2
7
8
TENC_EMIFA_AED48
CS
DQ0
16
WE
17
CAS
18
RAS
39
TENC_EMIFA_xABE7
DQMH
TENC_EMIFA_xABE6
15
DQML
37
36
CKE
NC1
JC312
0
38
40
CLK
NC2
IC304
MT48LC8M16A2P-75-Y15WTR
D_GND
F
G
1
2
D2S_3.3V
D_GND
CLKMODE[1:0]:Clock mode select
00 - Bypassx1
01 - x6
10 - x12
11 - Reserved
3
4
5
DSP-113 (3/20)
BOARD NO. 1-864-975-11, 12
NMX-170_DSP-113_014_3
H
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