Philips 47PFL5403 Service Manual page 61

Circuit Diagrams and PWB Layouts
SSB: Trident WX69
1 2 3 4
TRIDENT - WX69
B04A
A
7C01-3
SVP WX68
B
+3V3_SW 5C06
WX_PVCC
FC01 WX_PVCC
L4
PVCC
IC07 M5
33R ANTSTO
M4
AVCC1
N4
AVCC2
N5
AVCC3
WX_AVCC
P4
AVCC4
+3V3_SW L2
5C07
NC RXC-
FC02 WX_AVCC L1
RXC+
NC
L3
33R TMDS_GND1
C M3
TMDS_GND2
N3
TMDS_GND3
P3
TMDS_GND4
R1
TMDS_GND5
M2 TCLK1M B17
RX0-
M1
RX0+ TCLK1P
N2
RX1- TCLK2M
NC N1
RX1+ TCLK2P
P2
RX2-
P1
+3V3_SW 5C08
RX2+
FC03 WX_REGVCC WX_REGVCC
D R5
REGVCC
P5
33R DGND
T10
PWR5V
NC
T11
NC DSCL
U11
DSDA
NC
U12
WS
V11
SCDT
NC V12
SD0
+3V3_SW +3V3_SW +3V3_SW W11
AUDIOCLK
NC
W12
E SPDIF
NC Y11
SCK
IC14 IC15 IC16
F
+1V2_SW
5C09 FC04
+3V3_SW
+1V2_ADC
G
33R
5C10 FC05
+1V2_PLL
33R
H
5C11 FC06
+1V2_CORE
33R
I
+1V2_CORE
J
+2V5_VDDMQ
K
+3V3_SW
+2V5_VDDMQ +3V3_SW
5C12
FC07
WX_AVDD3_ADC1
L
33R
RES
WX_AVSS_ADC1
2C69
+3V3_SW
10u
5C13 FC08
WX_AVDD3_ADC2
33R NC
WX_AVDD3_ADC1
M WX_AVDD3_ADC2
+3V3_SW
WX_AVSS_ADC2 WX_AVDD3_OUTBUF
IXXX
5C14
33R FC09
WX_LVDS_VD D WX_AVDD3_BG_ASS
WX_PAVDD 1
WX_PAVDD 2
WX_AVDD_ADC1
WX_LVDS_VSS WX_AVDD_ADC2
WX_AVDD_ADC3
N +1V2_PLL WX_AVDD_ADC4
5C15 FC10 +1V2_PLL
WX_AVDDAPLL
WX_LVDS_VD D
33R
WX_AVDDAPLL
WX_AVDDLLPLL
WX_AVSSAPLL
+1V2_PLL
5C16 FC11
O WX_AVDDLLPLL
33R
WX_AVSSLLPLL
2C84 100p
2C85 100p 2C86 100p
P
2C87 100p 2C88 100p
2C89 100p
3139 123 6349.1
1 2 3 4
LC8.2A LA
5 6 7 8 9
Pin Name Pin No 1(HIGH)
WS U12 Use ALE to latch Address Use Falling Edges of WR#&RD# to latch Address(*)
SD0 V12 Use Rising Edge of WR# to latch data(*) Use Falling Edge of WR# to latch dat a
SCK Y11 I2C Slave Address=0x7E/7F(*) I2C Slave Address=0x7C/7 D
2C01 18p
3C02
33R
2C02 18p
WX_PAVDD 1 2C81 2n7
TxFPGAe_0p AD(0:7)
TA1P A14 WX_PAVDD 2 2C82 2n7
B14 TxFPGAe_0n AD(0) 3C04-1 1 8 100R
TA1M
A15 TxFPGAe_1p AD(1) 3C04-2 2 7 100R
TB1P
TxFPGAe_1n
B15 AD(2) 3C04-3 3 6 100R
TB1M
A16 TxFPGAe_2p AD(3) 3C04-4 4 5
100R
TC1P
B16 TxFPGAe_2n AD(4) 1 8 100R
3C05-1
TC1M
TxFPGAe_3p
A18 AD(5) 3C05-2 2 7 100R
TD1P
B18 TxFPGAe_3n AD(6) 3 6 100R
3C05-3
TD1M
A19 TxFPGAe_4p A(0:7) AD(7) 4 5
3C05-4 100R
TE1P
TxFPGAe_4n
B19 A(0) 3C06-1 1 100R 8
TE1M
TxFPGAe_CLKn
A(1) 3C06-2 2 7 100R
A17 TxFPGAe_CLKp A(2) 3C06-3 3 100R 6
F19 TxFPGAo_CLKn A(3) 3C06-4 4 100R 5
TxFPGAo_CLKp
E20 A(4) 3C03-4 4 5 100R
H19 TxFPGAo_4n A(5) 3 6
3C03-3 100R
TE2M
G20 TxFPGAo_4p A(6) 3C03-2 2 7 100R
TE2P
TxFPGAo_3n
G19 A(7) 3C03-1 1 100R 8
TD2M
TD2P F20 TxFPGAo_3p
ALE_EMU
E19 TxFPGAo_2n
WR
TC2M
TxFPGAo_2p
D20 RD
TC2P
B20 TxFPGAo_0n 100R
IIC_SDA_SIDE 3C08 IXXX
TA2M
A20 TxFPGAo_0p 3C09 100R
IIC_SCL_SIDE IXXX
TA2P
TxFPGAo_1n
D19 CS 3C10 22R IXXX
TB2M
C20 TxFPGAo_1p
TB2P
7C01-4
SVP WX68
C14 B3
VDDC1 VSS1
C15 C6 WX_AVDD3_OUTBUF IXXX
VDDC2 VSS2
D13 C9
VDDC3 VSS3
D14 C12
VDDC4 VSS4
D15 VSS5 D2
VDDC5
E13 H8 WX_AVSS_OUTBUF
VDDC6 VSS6
E14 H9
VDDC7 VSS7
E15 H10
VDDC8 VSS8
G16 H11
VDDC9 VSS9 IC03
H5 H12 WX_AVDD3_BG_ASS
VDDC10 VSS10
H16 H13
VDDC11 VSS11
J5 J8
VDDC12 VSS12
J16 J9
VDDC13 VSS13
K5 J10 WX_AVSS_BG_ASS
VDDC14 VSS14
K16 J11
VDDC15 VSS15
R16 J12
VDDC16 VSS16
T14 J13 WX_PAVDD 1
IXXX
VDDC17 VSS17
T15 K8
VDDC18 VSS18
B4 VSS19 K9
VDDM1
C4 K10
VDDM2 VSS20
WX_PAVSS1
D4 K11
VDDM3 VSS21
D5 K12
VDDM4 VSS22
D11 K13 WX_PAVDD 2
IXXX
VDDM5 VSS23
E5 L5
VDDM6 VSS24
E6 L8
VDDM7 VSS25
E9 L9
VDDM8 VSS26
E10 L10 WX_PAVSS2
VDDM9 VSS27
E11 L11
VDDM10 VSS28
E12 L12
VDDM11 VSS29
F5 L13
IC04
VDDM12 VSS30
G5 M8 WX_AVDD_ADC1
VDDM13 VSS31
L16 M9
VDDH1 VSS32
M16 VSS33 M10
VDDH2
N16 M11
VDDH3 VSS34
P16 M12 WX_AVSS_ADC1
VDDH4 VSS35
T12 M13
VDDH5 VSS36
T13 N8
VDDH6 VSS37
R17 N9
VDDH7 VSS38
R18 N10 WX_AVDD_ADC2
VDDH8 VSS39
P20 VSS40 N11
NC
Y3 N12
AVDD3_ADC1 VSS41
U9 N13
AVDD3_ADC2 VSS42
WX_AVSS_ADC2
U3 P18
AVDD3_OUTBUF VSS43
E2 T16
VDDR1 VSS44
E8 H20
VDDR2 VSS45
V3 Y2 WX_AVSS_OUTBUF
IC05
AVDD3_BG_ASS AVSS_OUTBUF
T3 VSSR1 E4 WX_AVDD_ADC3
PAVDD1
T4 E7
PAVDD2 VSSR2
U5 W3 WX_AVSS_BG_ASS
AVDD_ADC1 AVSS_BG_ASS
U7 T2 WX_PAVSS1
AVDD_ADC2 PAVSS1
T8 R3 WX_PAVSS2 WX_AVSS_ADC3
AVDD_ADC3 PAVSS2
U6 T5 WX_AVSS_ADC1
AVDD_ADC4 AVSS_ADC1
D18 T7 WX_AVSS_ADC2
LVDS_VDD P AVSS_ADC2
E17 AVSS_ADC3 T9 WX_AVSS_ADC3
LVDS_VDD A
D16 T6 WX_AVSS_ADC4 WX_AVDD_ADC4
LVDS_VDD D AVSS_ADC4
C17 E18
LVDS_VDDO1 LVDS_VSSP
D17 E16
LVDS_VDDO2 LVDS_VSSA
U1 C16 WX_LVDS_VSS
AVDDAPLL LVDS_VSSD
R2 C18 WX_AVSS_ADC4
AVDDLLPLL LVDS_VSSO 1
V5 C19
VREFN_1 LVDS_VSSO 2
W5 V1 WX_AVSSAPLL
VREFP_1 AVSSAPLL
V7 T1 WX_AVSSLLPLL
VREFN_2 AVSSLLPLL
W7
VREFP_2
5 6 7 8 9
7. 61
10 11 12 13
0(LOW)
7C01-1
SVP WX68
100n
W1 Y4 2C03 CVBS_RF
XTALI CVBS1
Y1 V6 2C04 100n HD_Y_IN
XTALO Y_G1
U2 W6 2C05 100n SC2_Y_CVBS_IN
MLF1 Y_G2
R4 Y_G3 Y6 2C06 100n SVHS_Y_CVBS_IN
PLF2
L17 W2 SC1_RF_OUT_CVBS
AD0 CVBS_OUT1
L18 V2 SC2_CVBS_MON_OUT
AD1 CVBS_OUT2
L19 V9 2C07 100n SVHS_C_IN
AD2 C
L20 W9 2C08 100n HD_PB_IN
AD3 PB_B1
K17 Y9 2C09 100n
SC1_B_IN
AD4 PB_B2
K18 Y10 2C10 100n SC1_CVBS_IN
AD5 PB_B3
K19 Y8 HD_PR_IN
2C11 100n
AD6 PR_R1
K20 W8
2C12 100n SC2_C_IN
AD7 PR_R2
N17 V8 2C13 100n
CVBS_IN_DTV
ADDR0 PR_R3
N18 FS1 V4 C? 100n
ADDR1 SC1_G_IN
N19 W4 100n
2C15 SC1_R_IN
ADDR2 FS2
N20 Y5 SC1_FBL_IN
ADDR3 FB1
M20 U4
ADDR4 FB2
NC
M19 V10 PC_VGA_H
ADDR5 AIN_H
M18 U10 PC_VGA_V
ADDR6 AIN_V
100n
M17 U8 2C17 VGA_R_IN
ADDR7 PC_R
J18 PC_G Y7 2C18 100n
VGA_G_IN
ALE
J19 W10 2C19 100n
VGA_B_IN
WR_ PC_B
J20 F17 3C19 470R
RD_ TESTMODE
H17 F16 3C20 1K0
SDA V5SF +3V3_STBY
H18 G17
SCL PWM0
+3V3_SW
J17 G18 SVPWX_INT
CPU_CS INTN
F18 4C07
SVPWX_RST
RESET
3C22 3C23
220R
FPGA_BL_DIMMING 4K7
IXXX
7C04
IC02
BC847BW
RES
IXXX
3C07
100R
IC01
3C25 10K
7C02
IC17
BC847BW
RES
2C73
10u
RES
4C08
Pin Name Pin No 1(HIGH) 0(LOW)
DP_HS P19 MPU in A/D Multiplix Mode MPU in A/D Separate Mode(*)
7C01-2
SVP WX68
DDR_VREF
+3V3_SW
WX_BA1
5C17 BA1
WX_BA0 K4
BA0
K3
33R
MVREF
WX_DQS3
E3
DQS3
WX_DQS2 B2
DQS2
WX_DQS1 B6
DQS1
WX_DQS0
B9
DQS0
+3V3_SW WX_CLKE B12
CLKE
WX_DQM3 K2
5C18
DQM3
WX_DQM2
B1
DQM2
WX_DQM1 A6
33R DQM1
WX_DQM0 A9
DQM0
WX_MCK0#
A12
MCK0_
WX_MCK0 IC09 E1
MCK0 DPB_HS
+3V3_SW D1
CS1_ DPB_VS
WX_CS0#
IC10 J3
3C46 CS0_ DPA_HS
WX_WE# IC11
J4
WE_ DPA_VS
WX_CAS# IC12 K1
22R
CAS_ DPB_DE
WX_RAS# IC13
J1
RAS_ DPA_CLK
WX_MD31
J2
MD31 DPB_CLK T19
WX_MD30 D3
MD30 DPA23
WX_MD29
C3
3C48 MD29 DPA22
WX_MD28
C2
MD28 DPA21
WX_MD27 C1
22R
MD27 DPA20
WX_MD26 A1
MD26 DPA19
WX_MD25
A2
MD25 DPA18
WX_MD24 A3
MD24 DPA17 W14
WX_MD23 C5
MD23 DPA16
+1V2_ADC WX_MD22
A4
MD22 DPA15
WX_MD21 B5
5C19
MD21 DPA14
WX_MD20 A5
MD20 DPA13
WX_MD19
D6
33R
MD19 DPA12
WX_MD18 A7
MD18 DPA11
WX_MD17 B7
MD17 DPA10 W16
WX_MD16
C7
MD16
WX_MD15 D7
MD15
+1V2_ADC WX_MD14 D8
MD14
WX_MD13
C8
5C20
MD13
WX_MD12 B8
MD12
WX_MD11 A8
33R MD11
WX_MD10
D9
MD10
WX_MD9
D10
MD9
WX_MD8 C10
MD8
WX_MD7
B10
MD7
+1V2_ADC WX_MD6
A10
MD6 DPB15
WX_MD5 A11
5C21
MD5 DPB14
WX_MD4 B11
MD4 DPB13
WX_MD3
C11
33R MD3 DPB12
WX_MD2 D12
MD2 DPB11
WX_MD1 A13
MD1 DPB10
WX_MD0
B13
MD0
WX_MA11 C13
MA11
+1V2_ADC WX_MA10 F1
MA10
WX_MA9
F2
5C22
MA9
WX_MA8 F3
MA8
WX_MA7 F4
33R MA7
WX_MA6
G4
MA6
WX_MA5
G3
MA5
WX_MA4 G2
MA4
WX_MA3
G1
MA3
WX_MA2
H1
MA2
WX_MA1 H2
MA1
WX_MA0
H3
MA0
H4
10 11 12 13
14 15 16 17
+5V_SW
+3V3_SW
7C03-1
74LCX14T
RES
3C30
1 2
3C31 22R
VGA_H
22R
7C03-2
74LCX14T
3C34
+5V_SW 3 4
22R
2C33
7C03-3
74LCX14T
100n
3C33
VGA_V 5 6
22R
7C03-4
74LCX14T
9 8
3C24 RES
BL_ADJUST_ANA
100R
RES
2C74
22u
3V04
BL_ADJUST_PWM
100R
+3V3_SW
VS NC
DP_HS
P17
IC18
HS P19
DP_HS
NC
V19
NC
V20 HDMI_H
HDMI_V
Y19
Y20 HDMI_DE
W20 HDMI_VCLK
Y15
NC
HDMI_Cr(9)
Y12 HDMI_Cr(8)
HDMI_Cr(7)
U13
V13 HDMI_Cr(6)
W13 HDMI_Cr(5)
Y13 HDMI_Cr(4)
Y14 HDMI_Cr(3)
HDMI_Cr(2)
V14 HDMI_Cb(9)
U14 HDMI_Cb(8)
U15 HDMI_Cb(7)
V15 HDMI_Cb(6)
W15 HDMI_Cb(5)
Y16 HDMI_Cb(4)
HDMI_Cb(3)
DPA9
V16 HDMI_Cb(2)
DPA8
U16 HDMI_Y(9)
DPA7
U17 HDMI_Y(8)
DPA6
V17 HDMI_Y(7)
DPA5
W17 HDMI_Y(6)
DPA4
HDMI_Y(5)
Y17
DPA3
HDMI_Y(4)
Y18
DPA2
W18 HDMI_Y(3)
DPA1
HDMI_Y(2)
V18
DPA0 W19
NC
U18
NC
U19 HDMI_Cb(1)
HDMI_Cb(0)
U20
T20 HDMI_Cr(1)
T18 HDMI_Cr(0)
T17 HDMI_Y(1)
DPB9 R19
HDMI_Y(0)
DPB8
R20
14 15 16 17
18 19 20
B04A
A
PC_VGA_H
B
PC_VGA_V
RES
3C36
C
22R
7C03-5 7C03-6
74LCX14T 74LCX14T
3C37
11 10 13 12
22R
D
E
F
G
H
I
J
K
L
M
N
"C00-"C99" & "V00 - V99"
MULTI 12NC : 3139_123_63481
SINGLE 12NC : 3139_123_63491
O
P
I_17760_005.eps
180208
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