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RX-8010RBK/ RX-8012RSL
Description of major ICs
AK4112AVF (IC551) : Digital audio receiver
1.Pin layout
DVDD
28
1
DVSS
27
2
TVDD
3
26
V/ TX
25
4
XTI
5
24
XTO
23
6
PDN
22
7
R
8
21
AVDD
20
9
AVSS
10
19
RX1
18
11
RX2/ DIF0
17
12
RX3/ DIF1
13
16
RX4/ DIF2
15
14
1-12
2.Pin function
No.
Pin Name
CM0/ CDTO
1
DVDD
CM1/ CDT1
2
DVSS
OCKS1/ CCLK
OCKS0/ CSN
3
TVDD
MCKO1
4
V
MCKO2
TX
DAUX
5
XTI
BICK
6
XTO
SDTO
7
PDN
LRCK
ERF
8
R
FS96
P/ SN
AUTO
9
AVDD
10
AVSS
11
RX1
12
DIF0
RX2
13
DIF1
RX3
14
DIF2
RX4
15
AUTO
16
P/S
17
FS96
18
ERF
19
LRCK
20
SDTO
21
BICK
22
DAUX
23
MCK02
24
MCK01
25
OCKS0
CSN
26
OCKS1
CCLK
27
CM1
CDTI
28
CM0
CDTO
Note 1 : All input pins except internal pull-down pins should not be left floating.
Digitized in Heiloo the Netherlands
I/O
Function
-
Digital power supply pin, 3.3V
-
Digital ground pin
-
Input buffer power supply pin, 3.3V or 5V
O
Validity flag output pin in Parallel Mode
O
Transmit channel (through data) output pin in Serial Mode
I
X'tal input pin
O
X'tal output pin
I
Power-down mode pin
When "L", the AK4112A is powerd-down and reset.
-
External resistor pin
18k
+/-1% resistor to AVSS externally.
-
Analog power supply pin
-
Analog ground pin
I
Receiver channel 1
This channel is selected in Parallel Mode or default of Serial Mode.
I
Audio data interface format 0 pin in Parallel Mode
I
Receiver channel 2 in Serial Mode
I
Audio data interface format 1 pin in Parallel Mode
I
Receiver channel 3 in Serial Mode
I
Audio data interface format 2 pin in Parallel Mode
I
Receiver channel 4 in Serial Mode
O
Non-PCM detect pin
"L" : No detect, "H" : Detect
I
Parallel/ Serial select pin
"L" : Serial Mode, "H" ; Parallel Mode
O
96kHz sampling detect pin
(RX Mode) "H" : fs=88.2kHz or more, "L" fs=54kHz or less.
(X'tal Mode) "H" : XFS96=1, "L" : XFS96=0.
O
Unlock & parity error output pin
"L" : No error, "H" : Error
I/O
Output channel clock pin
O
Audio serial data output pin
I/O
Audio serial data clock pin
I
Auxiliary audio data input pin
O
Master clock #2 output pin
O
Master clock #1 output pin
I
Output clock select 0 pin in Parallel Mode
I
Chip select pin in Serial Mode
I
Output clock select 1 pin in Parallel Mode
I
Control data clock pin in Serial Mode
I
Master clock operation Mode pin0 in Parallel Mode
I
Control data input pin in Serial Mode
I
Master clock operation Mode pin1 in Parallel Mode
O
Control data output pin in Serial Mode
2/17/2019
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