Note On Using Watchdog Timer - Fujitsu F2MC-8FX MB95200H/210H Series Application Note

5 Note on Using Watchdog Timer

Take account of the following points when using the watchdog timer.
Stopping the watchdog timer
Once activated, the watchdog timer cannot be stopped until a reset is generated.
If a HWWDT is select, it will resume operation after a reset.
Selecting the count clock
Software watchdog timer
The count clock switch bits (WDTC: CS1, CS0, CSP) can be rewritten only when the
watchdog control bits (WDTC: WTE3 to WTE0) are set to "0101B" upon the
activation of the watchdog timer. The count clock switch bits cannot be written by a
bit operation instruction. Moreover, the bit settings should not be changed once the
timer is activated.
In sub-clock mode, the timebase timer does not operate because the main clock
stops oscillating.
In order to operate the watchdog timer in sub-clock mode, it is necessary to select
the watch prescaler as the count clock beforehand and set "WDTC: CS1, CS0, CSP"
to "100 " or "110
B
Hardware watchdog timer
The count clock is fixed at 2
Clearing the watchdog timer
Clearing the counter used for the count clock of the watchdog timer (timebase timer
or watch prescaler or sub-CR timer) also clears the counter of the watchdog timer.
The counter of the watchdog timer is cleared when entering the sleep mode, stop
mode or watch mode except in the case of selecting the hardware activation with the
hardware watchdog timer running in a standby mode.
Programming precaution
When creating a program in which the watchdog timer is cleared repeatedly in the
main loop, set the processing time of the main loop including the interrupt processing
time to the minimum watchdog timer interval time or shorter.
Hardware watchdog (with timer running in a standby mode)
The watchdog timer does not stop in stop mode, sleep mode, timebase timer mode
or watch mode. Therefore, the watchdog timer is not to be cleared by the CPU even
if the internal clock stops. (in stop mode, sleep mode, timebase timer mode or watch
mode).
Regularly release a standby mode and clear the watchdog timer. However, a
watchdog reset may be generated depending on the setting of the oscillation
stabilization wait time setting register after the CPU returns from stop mode in sub-
clock mode or sub-CR mode.
Take account of the setting of the sub-clock stabilization wait time when selecting the
sub-clock.
WATCHDOG TIMER V1.1
Chapter 5 Note on Using Watchdog Timer
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