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4.3 Hardware watchdog timer
The hardware watchdog timer is set up through the following procedure:
1) Activate the watchdog timer by writing "A597
mode) or any other value (WDT is enabled in every mode) except other than "A596
and "A597
" to the address FFBE
H
copied to the watchdog timer selection ID register WDTH/WDTL (0FEB
2) The HWWDT starts automatically after a reset.
3) Clear the watchdog timer with minimum interval time. (WDTC:WTE3 to WTE0 =
0101
)
B
Cause of while using the HWWDT, the count clock switch bits: CS1, CS0, CSP are
fixed at "001", the interval time is fixed at 2
The following example shows how to set watchdog timer for operating in hardware mode.
/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS.
/* FUJITSU MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY
/* FOR ANY ERRORS OR ELIGIBILITY FOR ANY PURPOSES.
/*
(C) Fujitsu Microelectronics (Shanghai) Co., LTD.
/* Date: 20080320
/*--------------------------------------------------------------------*/
/* Hardware watchdog timer starts automatically after a reset and */
/* cannot be stopped. The internal time is fixed to 2
/* main routine */
void
main (void)
{
...
WDTC |= 0x05;
...
}
;------------------------------------------------------------------------
; Hard Watchdog
;------------------------------------------------------------------------
; #define HWD_DISABLE
#ifdef
HWD_DISABLE
.SECTION
#endif
main.c
startup.asm
Refer to Appendix Sample Code for project "HWWDT".
Please note that the hardware watchdog timer starts automatically after a reset and cannot
stop its operation.
WATCHDOG TIMER V1.1
Chapter 4 Usage and Examples
H
Version: 1V0
// clear WDT counter
WDT, CONST, LOCATE=H'FFBE
.DATA.W
0xA596
MCU-AN-500013-E-11 – Page 11
" (WDT is enabled except in standby
H
and FFBF
on the flash memory, which are
H
16
/F
too.
CRL
Author: Levi
16
/0FEC
)
H
H
/FCRL
*/
"
H
*/
*/
*/
*/
*/
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