MSI KM4M Series Manual page 53

MS-6734 M-ATX Mainboard
Current FSB/DRAM/DDR Frequency
These items show the current FSB/DRAM/DDR frequency. (read only)
DRAM Clock
This item is used to configure the clock frequency of the installed DRAM.
Settings: By SPD, 100MHz, 133MHz, 166MHz.
DRAM Timing
Selects whether DRAM timing is controlled by the SPD (Serial Presence
Detect) EEPROM on the DRAM module. Setting to By SPD enables
DRAM timings to be determined by BIOS based on the configurations on
the SPD. Selecting Manual allows users to configure the DRAM timings
manually. Options: By SPD, Manual, Turbo, Ultra.
DRAM CAS Latency
When synchronous DRAM is installed, the number of clock cycles of
CAS latency depends on the DRAM timing. The settings are: 1.5, 2, 2.5,
3.
Bank Interleave
This field selects 2-bank or 4-bank interleave for the installed SDRAM.
Disable the function if 16MB SDRAM is installed. Settings: Disabled, 2
Bank and 4 Bank.
Precharge To Active (tRP)
This item controls the number of cycles for Row Address Strobe (RAS) to
be allowed to precharge. If insufficient time is allowed for the RAS to
accumulate its charge before DRAM refresh, refresh may be incomplete
and DRAM may fail to retain data. This item applies only when synchro-
nous DRAM is installed in the system. Available settings: 2T, 3T.
Trans Non-DDR400/DDR400
This controls the timing delay (in clock cycles) before non-DDR400 and
DDR400 starts a write command after receiving it. Settings: 6T/8T, 7T/
10T, 5T/6T, 8T/12T. 12T increases the delay time while 5T provides the
least timing delay. This option is effective only if DDR400 is running.
Active to CMD (Trcd)
When DRAM is refreshed, both rows and columns are addressed
3-12