LG KT520 Service Manual page 78

A. Transmitter Part
Polar modulation transmitter architecture based on the direct phase/frequency modulation/synthesizer
architecture is implemented for GSM, GPRS and EDGE. This architecture has the capability of
generating both the GSM/GPRS constant envelope GMSK modulation and the linear EDGE 8-PSK
modulation in a very cost efficient way. The motivation for a polar modulation transmitter architecture
compared to traditionally linear architectures is to reduce the output noise (thus eliminating the need
for off-chip filters) reduce the power consumption by utilizing non-linear switching analog signal
processing blocks, and to eliminate the need for an RF isolator.
The transmitter block consists of several sub-blocks: A separate block is used to convert the digital bit
streams from the baseband into parallel words to be used in the DACs and the Sigma Delta modulator.
The combined DAC and LP-filter is used to convert the digital words of the digital block into analog
signals. The second FM-path is used to add the high frequency part of the FM to the VCO. It also
includes an auto-tuning block that compensates VCO gain variations.
In the Sigma Delta modulator block, the phase/frequency modulator in this polar modulation
architecture is a sigma-delta controlled fractional-N frequency synthesizer with an additional frequency
insertion point after the loop filter at the input of the VCO. In addition, The TX-buffer is used to drive
the PA with the correct power level. A divide by 2 or 4 block is used to generate the correct output
frequency from the 4 GHz VCO. The phase locked loop has two information inputs:
the divider ratio in the feedback path and a direct path to the VCO. The phase locked loop generates
the radio frequency carrier including the phase modulation information at the desired channel
frequency.
B. Receiver part
Direct down-conversion zero-IF receiver architecture is used for the four EDGE/GSM/GPRS frequency
bands 800, 900, 1800 and 1900 MHz. The complete receiver with four Low Noise Amplifiers (LNAs),
one for each supported band, is integrated on chip. After the down-conversion, the in-phase and
quadrature-phase components are low pass filtered with two anti-alias filters before the signals are fed
to the integrated high dynamic range sigma-delta A/D-converters. The only required external
components are the band selectivity SAW filters in front of the LNAs. One filter is required per
supported frequency band. The digital output signals are sent over a serial interface to the digital base-
band circuit for further processing and detection.
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3. TECHNICAL BRIEF
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