LG KT520 Service Manual page 37

3. TECHNICAL BRIEF
■ HW support for packet types
- ACL: DM1, DM3, DM5, DH1, DH3, DH5, 2-DH1, 2-DH3,2-DH5,3-DH1,3-DH3, 3-DH5
- SCO: HV1, HV3 and DV
- eSCO: EV3, EV4, EV5, 2-EV3, 2-EV5, 3-EV3, 3-EV5
■ Clock support
- System clock input (digital or sine wave) at 9.6, 10, 13, 16, 16.8, 19.2, 26, 33.6 or 38.4MHz
- LP clock input at 3.2, 16.384, 32 or 32.768 kHz
■ ARM7TDMI CPU
- 32-bit Core
- AMBA (AHB-APB) bus configuration
■ Patch RAM capability
■ Memory organization
- On chip RAM, including provision for patches
- On chip ROM, preloaded with FW up to HCI
■ Communication interfaces
- Fast UART up to 4Mbit/s
- SPI interface
- PCM/I2S interface
- Up to 10 additional flexibly programmable GPIOs
- External interrupts possible through the GPIOs
- Fast master I2C interface
■ Efficient and flexible support for WLAN coexistence in collocated scenario
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