LG KT520 Service Manual page 27

3. TECHNICAL BRIEF
D. DSP Hardware Subsystem
The Digital Signal Processor Subsystem (DSPSUB) includes a DSP megacell, which contains the DSP
CPU together with a tightly coupled memory. The DSP is the Ceva-X 1620 core with a 64 kB
instruction RAM and a 64 kB data RAM. It also contains debug logic and interfaces. In addition to the
megacell, the DSPSUB includes external memories, peripheral units, and interfaces. The DSP
megacell is clocked at 208 MHz.
The DSPSUB includes an AHB master and an AHB slave interface. The AHB master provides a direct
access to the Internal Random Access Memory (IRAM) in the EGG core through the AHB. The AHB
slave interface allows the CPU and the DMA to access in the program and data RAM residing in the
DSPSUB.
E. XGAM Subsystem
The XGAM subsystem is a graphics acceleration module that provides hardware support in the
creation of visual imagery and the transfer of this data to a display. The XGAM also provides support
for connecting a Camera module. The visual data could be graphics, still images, or video.
The XGAM subsystem is handled and provided by Ericsson.
F. System Control Subsystem
The SYSCON resides at the top level of the circuit architecture and is responsible for clock generation
and clock and reset distribution within the digital baseband controller, as well as to external devices.
The block is a slave peripheral under control of the ARM processor. The programming of the SYSCON
controls the fundamental modes of operation within the digital baseband controller. Individual blocks
can also be reset and their clocks held inactive by accessing the appropriate control registers.
LGE Internal Use Only Copyright © 2008 LG Electronics. Inc. All right reserved.
- 28 -
Only for training and service purposes