Nokia 8208 Service Manual page 137

RM-384
System Module and User Interface
Modes of operation
Mode
Power-off
Sleep
IDLE
POWER UP
POWER DOWN
STANDBY
POWER-ON-RESET
Issue1
In power-off mode, power (VPH_PWR) is supplied to the PM, RF PA,
vibrator, and keypad backlight LED. During this mode, the current
consumption is approximately 6.967uA.
PMU will enter into SLEEP mode from IDLE mode when TCXO_EN is LOW.
In SLEEP mode the quiescent current is minimized in order to extend
phone's standby time. Sum of load currents of Buck1, Buck2, LDO1,
LDO2 and LDO4 should stay below 5mA in SLEEP mode. All LDO's
enabled by Serial Interface will stay on in SLEEP mode. Transition from
SLEEP mode to POWER DOWN mode is the same as defined for IDLE
mode.
PMU will enter into IDLE mode (normal operating mode) after PS_HOLD
signal is asserted by the host processor. IDLE mode will enable all PMU
functions that can be controlled by the Serial Interface or direct control
inputs.
PS_HOLD going low or a flag failure >60 ms in any of Buck1, Buck2,
LDO1, LDO2 and LDO4 output voltages will initiate a Power Down
Sequence.
If a flag failure in IDLE mode will last less than 60 ms, RESET_N will be
asserted, the status bit FF will be set and PMU will step back in POWER UP
mode without shutting down the voltage outputs. Two such flag
failures will cause a Power Down. Host processor can use the FF bit to
start up the phone without user interference in case of flag failure.
POWER UP mode will be activated by a Power-on-Switch (PWR_ON) or
HF_PWR signal or the insertion of a charger input voltage (CHG_IN).
During the Power Up Sequence output voltages MSMC (Buck1),
MSME (Buck2), MSMP (LDO1), MSMA (LDO4) and LCD (LDO2) will be
activated in a sequence and with default voltages determined by the
status of the SEL1 and B2_EN control inputs. Reset (RESET_N) will be
released in order to power the host processor up properly.
A flag failure >60 ms, or an Under Voltage lockout, or improper timing
on PS_HOLD during POWER UP mode will start a Power Down sequence.
In POWER DOWN mode a reset (RESET_N) will be asserted and all supply
voltages will be turned off in a correct sequence to ensure proper shut
down of the host processor. As a default, outputs of LDO1, LDO2, LDO4 and
Buck2 are pulled down. In POWER DOWN mode all internal registers are
reset to the default values.
In STANDBY mode all PMU functions are disabled and PMU is in low power
condition.
In POWER-ON-RESET mode Power on Reset (POR) is HIGH and all internal
registers are reset to the default values.
Table 29 Mode of operation
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