Block Diagram And Circuit Description - Sony HDW-250 Maintenance Manual

Hd digital videocassette recorder
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Outline
The unit records and plays back the video signal and audio
signal on a magnetic tape with the HD CAM format.
Acoustic noise is reduced by decreasing the number of
drum rotation to 1/2 of the studio VTR and by increasing
the number of recording heads 2 times (8 heads).
Record System
The video signal input and the audio signal input are either
one of the followings:
Video input signal
. Analog component input signal (Y/P
. HD SDI (SMPTE-292M/BTA S-004B;Serial Digital)/
Audio input signal
. Analog audio (LINE, Camera MIC)/
. HD SDI (SMPTE-292M/BTA S-004B;Serial Digital)/
The analog video signal that is input to the CC-82 board, is
buffered and sent to the VPR-53 board. Either the analog
video input signal or the HD SDI input signal after it is
converted to A/D, is selected in accordance with the
operating mode being used.
The selected signal is bandwidth compressed from 4:2:2 →
3:1:1 by the FIL IC. The signal receives the bit rate
reduction by the HENC so that that input video signal is
compressed to about 1/7. The outer and inner ECC are
added to the compressed video signal by the ECC IC to
generate the HD CAM format video signal. Four channels
of the HD CAM format video signal are sent to the EQ-76
board.
On the other hand, the analog audio input signal is A/D
converted by the ADA-44 board and sent to the audio
processor of the DPR-53 board.
The outer ECC is added to the audio data output from the
audio processor, by the ECC IC so that the audio signal
conforming to the HD CAM format in which the audio
signal is inner-coded inside the video compressed data, is
generated. The audio signal of the HD CAM format is sent
to the EQ-76 board.
During the cue channel recording, the analog audio signals
of channel 1 to channel 4 are mixed to form the cue signal.
HDW-250
Section 4

Block Diagram and Circuit Description

/P
)/CAMERA 26P
B
R
BNC
XLR-3P, CAMERA 26P
BNC
.
Playback System
The playback RF signal that is supplied from the head
drum, is converted to the four-channel serial PB data by
the PB equalizer and the Viterbi decoder of the EQ-76
board. The four channel serial PB data is input to the DE
IC as they are, where the data receives the inner correction
first then receives the outer correction of both video and
audio signals. After corrections, the video signal is sent to
the HDEC IC while the audio signal is sent to the AP5 IC.
The video data is restored by the HDEC IC where the bit
rate reduced video signal is restored to the video signal of
the original bit rate. The video signal after restoration has
the bandwidth of 3:1:1 that is input to the subsequent CNC
IC. In the CNC IC, the un-correctable signal in units of
correction block receives the error concealment.
The video signal is sent to the subsequent FIL IC where
data is converted from 3:1:1 → 4:1:1. Output signal from
the converter is sent to the analog component system and
to the down converter output system where video and
audio signals are output after respective signal processing.
The audio output signal from the DE IC, is sent to AP5
where the signal receives the required audio processing
and rate conversion. The audio signal is then D/A convert-
ed so that the analog audio signal is sent to the analog
LINE OUT system and to the output system in which the
audio signal is embedded to the HD SDI output. The video
and audio signals are output from the respective signal
systems.
System Control and Servo Systems
The system control receives the commands from the front
panel, camera and external equipment as they are operated,
and controls the entire system of the unit and controls its
operations.
The unit has the three built-in CPUs for the system control,
servo control and camera respectively. Data transfer
between the three CPUs is accomplished by the dual port
RAM.
The system control CPU is the 32-bit CPU operating on
the 27 MHz clock. The servo CPU is the 16-bit CPU
operating on the 20 MHz clock. Peripheral circuits of
these CPUs are built inside the CPUs so that external
circuit is minimized.
4-1

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