Register Table - Epson RX801SJ Applications Manual

Real time clock module
Table of Contents

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RX8010 SJ

12.2. Register table

Address [h]
10
11
12
13
14
15
16
17
Setting data
18
HOUR Alarm
19
WEEK Alarm
1A
Timer Counter 0
1B
Timer Counter 1
1C
Extension Register
1D
Flag Register
1E
Control Register
1F
Setting data
Address [h]
20
|
2F
Address [h]
30
Setting data
31
Setting data
32
Setting data
Note
During the initial power-on (from 0 V) and if the value of the VLF bit is "1" when the VLF bit is read, be sure to
initialize all registers before using them.
When doing this, be careful to avoid setting incorrect data as the date or time, as timed operations cannot be
guaranteed if incorrect date or time data has been set.
∗1.
During the initial power-on (from 0 V), the power-on reset function sets "1" to the VLF bit.
∗ Since the value of other registers is undefined at this time, be sure to reset all registers before using them.
∗2.
The TEST, bit are Epson test bits.
∗ Be sure to write "0" by initializing before using the clock module. Afterward, be sure to set "0" when writing.
∗ The four
TEST*
bits are undefined when read. Those bits should be masked after being read.
∗3.
The '
' mark indicates a write-prohibited bit, which returns a "0" when read.
∗4.
The ' • ' mark indicates a read/write-accessible RAM bit for any data.
∗5.
The '-' mark is a Reserved bit. It is necessary to write in
∗6.
User Register is a free register.
Function
bit 7
SEC
MIN
HOUR
WEEK
DAY
MONTH
YEAR
80
Reserved
-
1
MIN Alarm
AE
AE
AE
DAY Alarm
128
32768
FSEL1
TEST
0
Function
bit 7
RAM
Function
bit 7
Reserved
-
0
Reserved
0
IRQ Control
0
bit 6
bit 5
bit 4
40
20
10
40
20
10
20
10
6
5
4
20
10
10
40
20
10
-
-
-
1
0
1
40
20
10
20
10
6
5
4
20
10
64
32
16
16384
8192
4096
FSEL0
USEL
TE
UF
TF
STOP
UIE
TIE
STOP
UIE
TIE
bit 6
bit 5
bit 4
User Register
128 bit ( 16 word x 8 bit )
bit 6
bit 5
bit 4
-
-
-
0
0
0
-
0
0
0
-
-
-
0
0
0
Setting data
at the time of initialization.
Page − 12
bit 3
bit 2
bit 1
8
4
2
8
4
2
8
4
2
3
2
1
8
4
2
8
4
2
8
4
2
-
-
-
1
0
0
8
4
2
8
4
2
3
2
1
8
4
2
8
4
2
2048
1024
512
WADA TSEL2 TSEL1 TSEL0
AF
VLF
AIE
TSTP
-
AIE
TSTP
0
bit 3
bit 2
bit 1
bit 3
bit 2
bit 1
-
-
-
0
0
0
-
-
-
1
0
0
TMPIN
FOPIN1 FOPIN0
0
TMPIN
FOPIN1 FOPIN0
ETM37E-06
bit 0
1
1
1
0
1
1
1
-
0
1
1
0
1
1
256
-
0
bit 0
bit 0
-
0
-
0

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