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RX - 4803 SA / LC
8. Use Methods
8.1. Description of Registers
8.1.1. Write / Read and Bank Select
R/W and Register bank are specified by the four bits mode setting code.
Bank1: Basic time and calendar register
Bank2: Extension register
Bank3: Extension register
Mode
Read
Write
The register of the same name of Bank1 and Bank2 is the same register.
8.1.2. Register table (Bank1)
Address
Function
0
SEC
1
MIN
2
HOUR
3
WEEK
4
DAY
5
MONTH
6
YEAR
7
RAM
8
MIN Alarm
9
HOUR Alarm
WEEK Alarm
A
DAY Alarm
B
Timer Counter 0
C
Timer Counter 1
D
Extension Register
E
Flag Register
F
Control Register
Note
When after the initial power-up or when the result of read out the VLF bit is "1" , initialize all registers, before
using the module.
Be sure to avoid entering incorrect date and time data, as clock operations are not guaranteed when the data
or time data is incorrect.
∗1)
During the initial power-up, the TEST bit is reset to "0" and the VLF bit is set to "1".
∗ At this point, all other register values are undefined, so be sure to perform a reset before using the module.
∗2)
Only a "0" can be written to the UF, TF, AF, VLF, or VDET bit.
∗3)
Any bit marked with "
∗4)
Any bit marked with "•" is a RAM bit that can be used to read or write any data.
∗5)
The TEST bit is used by the manufacturer for testing. Be sure to set "0" for this bit when writing.
...
Bank1 is compatible with RX-4801.
... Adds 1/100s Counter.
... Capture buffer and Event control registers.
Bank 1
Bank 2
9 h
A h
1 h
2 h
bit 7
bit 6
40
40
6
80
40
•
•
AE
40
•
AE
6
AE
•
128
64
•
•
TEST WADA USEL
CSEL1 CSEL0
" should be used with a value of "0" after initialization.
Bank 3
B h
3 h
bit 5
bit 4
bit 3
bit 2
20
10
8
4
20
10
8
4
20
10
8
4
5
4
3
2
20
10
8
4
10
8
4
20
10
8
4
•
•
•
•
20
10
8
4
20
10
8
4
5
4
3
2
20
10
8
4
32
16
8
4
•
•
2048
1024
TE
FSEL1 FSEL0 TSEL1 TSEL0
UF
TF
AF
EVF
UIE
TIE
AIE
EIE
Page - 6
bit 1
bit 0
Read
Write
P
2
1
2
1
P
P
2
1
P
1
0
2
1
P
P
2
1
P
2
1
•
•
P
P
2
1
P
2
1
1
0
P
2
1
P
2
1
512
256
P
P
P
VLF
VDET
RESET
P
P : Possible , I : Impossible
ETM33E-04
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
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