Register Table - Epson RX8130 CE Applications Manual

Real time clock module
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RX8130CE

13.2. Register table

13.2.1. Register table
Address[h]
10
11
12
13
14
15
16
17
18
HOUR Alarm
WEEK Alarm
19
1A
Timer Counter 0
1B
Timer Counter 1
1C
Extension Register
1D
Flag Register
1E
Control Register0
1F
Control Register1
Address[h]
20
|
23
Address[h]
30
Digital offset
1.
After the initial power-up (from 0V) or in case the VLF bit returns "1" , make sure to initialize all registers,
before using the RTC.
Be sure to avoid entering incorrect date and time data, as clock operations are not guaranteed when the data or
time data is incorrect.
2.
The TEST bit is used by the manufacturer for testing. Be sure to set "0" for this bit when writing.  Be sure to
write "0" by initializing before using the clock module. Afterward, be sure to set "0" when writing
3.
Any bit marked with "
4.
Any bit marked with "•" is a RAM bit that can be used to read or write any data.
5.
User Register is a free register which can be used as user RAM.
6.
The above table shows only the user registers. Due to functional reasons, RTC has different registers not
mentioned above table which are programmed by the manufactorer. Please make sure to only access above
mentioned user registers.
Function
bit 7
SEC
MIN
HOUR
WEEK
DAY
MONTH
YEAR
80
MIN Alarm
AE
AE
AE
DAY Alarm
128
32768
FSEL1 FSEL0
VBLF
TEST
SMP
TSEL1
Function
bit 7
RAM
Function
bit 7
DTE
" should be used with a value of "0" after initialization
bit 6
bit 5
bit 4
40
20
10
40
20
10
20
10
6
5
4
20
10
10
40
20
10
40
20
10
20
10
6
5
4
20
10
64
32
16
16384
8192
4096
USEL
TE
UF
TF
STOP
UIE
TIE
SMP
CHG
INIEN
TSEL0
EN
bit 6
bit 5
bit 4
User Register
32 bit ( 4 word x 8 bit )
bit 6
bit 5
bit 4
L7
L6
L5
Page14
bit 3
bit 2
bit 1
8
4
2
8
4
2
8
4
2
3
2
1
8
4
2
8
4
2
8
4
2
8
4
2
8
4
2
3
2
1
8
4
2
8
4
2
2048
1024
512
WADA TSEL2 TSEL1 TSEL0
AF
RSF
VLF
AIE
TSTP
TBKON TBKE
RS
BF
VSEL
VSEL1
bit 3
bit 2
bit 1
bit 3
bit 2
bit 1
L4
L3
L2
ETM50E-05
bit 0
1
1
1
0
1
1
1
1
1
0
1
1
256
VBFF
BF
VSEL0
bit 0
bit 0
L1

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