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TC4S71F (TOSHIBA)CHIP PACKAGE
TC7S32FU(TE85R) (TOSHIBA)FLAT PACKAGE
TC4S71F(TE85R)
C-MOS 2-INPUT OR GATE
-TOP VIEW-
2
A
4
1
5 V
DD
1
B
2
GND 3
4
Y = A + B = A • B
A
B
Y
0
0
0
0
1
1
1
0
1
0 ; LOW LEVEL
1
1
1
1 ; HIGH LEVEL
TYPE
7S32F
7S32FU
4S71F
7SH32FU
TC4SU69F (TOSHIBA)CHIP PACKAGE
TC7S04FU(TE85R) (TOSHIBA)FLAT PACKAGE
TC4SU69F(TE85R)
C-MOS INVERTER
-TOP VIEW-
1
5 V
2
4
DD
A
A
Y =
2
Y = A
GND 3
4
A
Y
0
1
1
0
V
TYPE
DD
0 ; LOW LEVEL
1 ; HIGH LEVEL
7S04F
7SU04F
+2 to +6V
7SU04FU
4S69F
+3 to +18V
4SU69F
7SH04FU
+2 to +5.5V
7SHU04FU
TC74VHC541FS(EL) (TOSHIBA)FLAT PACKAGE(SMALL)
C-MOS BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
- TOP VIEW -
G2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
20
19
18
17
16
15
14
13
12
V
DD
1
2
3
4
5
6
7
8
9
G1
A1
A2
A3
A4
A5
A6
A7
A8
2
18
3
17
NOTE :
4
16
TYPE
5
15
TC74AC/TC74VHC
+2 to +5.5V
6
14
ABT/ACT/BCT/HCT/VHCT
7
13
OTHER TYPES
8
12
9
11
G1
G2
1
19
CA-755/755P
A
Y
Y =
B
V
DD
+2 to +6V
+3 to +18V
+2 to +5.5V
Y
Y8
A
Y
11
G1
G2
G1
G2
A
Y
0
0
0
1
0
0
1
0
GND
1
X
X
HI-Z
10
X
1
X
HI-Z
0 ; LOW LEVEL
1 ; HIGH LEVEL
X ; DON'T CARE
HI-Z ; HIGH IMPEDANCE
V
DD
+5V
+2 to +6V
TC4W53FU (TOSHIBA)CHIP PACKAGE
TC4W53FU(TE12R)
C-MOS 2-CHANNEL MULTIPLEXER / DEMULTIPLEXER
(SCALE 3/1)
6
ch1
—TOP VIEW—
7
ch0
1
OPEN
8 V
DD(+3 to +18V)
5
A
2
7
INH
3
6
2
GND 4
5
CONT.INPUT
ON
INH
A
CHANNEL
0
0
0
ch
0 ; LOW LEVEL
0
1
1
ch
1 ; HIGH LEVEL
1
X
OPEN
X ; DON'T CARE
TC74VHC32FS(EL) (TOSHIBA)FLAT PACKAGE(SMALL)
C-MOS QUAD 2-INPUT OR GATES
-TOP VIEW-
14
13
12
11
10
9
8
V
DD
GND
1
2
3
4
5
6
7
NOTE:
TYPE
V
DD
74AC/74VHC
+2 to +5.5V
74HC
+2 to +6V
74HCT
+4.5 to +5.5V
TC74VHC574FS(EL) (TOSHIBA)FLAT PACKAGE(SMALL)
C-MOS 3-STATE D-TYPE EDGE-TRIGGERED FLIP-FLOP
-TOP VIEW-
2
EN
1
V
20
IN
DD
3
4
D1
2
19
Q1
IN
OUT
5
6
D2
3
18
Q2
IN
OUT
7
8
D3
4
17
Q3
IN
OUT
9
11
D4
5
16
Q4
IN
OUT
D5
6
15
Q5
IN
OUT
D6
7
14
Q6
IN
OUT
D7
8
13
Q7
IN
OUT
D8
9
12
Q8
IN
OUT
10
GND
11
CK
IN
D1
Q1 D2
Q2 D3
Q3 D4
2
19
3 18
4 17
5 16
D Q
Q
EN
11
CK
1
EN
NOTE;
TYPE
V
DD
74HC
+2 to +6V
74AC/74VHC
+2 to +5.5V
74ACT/74FCT/74HCT
+4.5 to +5.5V
+2 to 3.6V
74LCX
+2.7 to 3.6V
74LVC
1
C
V
EE
3
A
A
Y =
Y
B
B
Y = A + B = A • B
A
B
Y
0
0
0
0
1
1
1
0
1
1
1
1
0 ; LOW LEVEL
1 ; HIGH LEVEL
EACH FLIP-FLOP
19
D1
Q1
INPUTS
OUT
18
D2
Q2
EN
CK
D
Q
17
D3
Q3
0
1
1
16
D4
Q4
0
0
0
15
D5
Q5
X
0
Q
14
0
D6
Q6
X
X
1
HI-Z
13
D7
Q7
12
0
; LOW LEVEL
D8
Q8
1
; HIGH LEVEL
X
; DON'T CARE
EN
HI-Z
; HIGH IMPEDANCE
1
Q
; NO CHANGE
0
Q4 D5
Q5 D6
Q6 D7
Q7 D8
Q8
6 15
7 14
8 13
9
12
D
Q
Q
EN
4-17
IC
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