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IC
CY7B923-JC (CYPRESS)
BIC-MOS TRANSMITTER
—TOP VIEW—
4
3
2
1
28 27 26
5
6
7
8
9
10
11
12 13 14 15 16 17 18
PIN
PIN
I/O
SIGNAL
I/O
NO.
NO.
1
O
OUT B_
15
I
2
O
OUT C_
16
I
3
O
OUT C+
17
I
4
—
V
18
I
DD
5
I
BISTEN
19
I
6
—
GND
20
—
7
I
MODE
21
I
8
O
RP
22
—
9
—
V
23
I
DD
10
I
SVS(D
)
24
I
J
11
I
D7(D
)
25
I
H
12
I
D6(D
)
26
O
G
13
I
D5(D
)
27
O
F
14
I
D4(D
)
28
O
I
10
SVS(D
)
J
19
SC/D(D
)
A
18
D0(D
)
B
17
D1(D
)
C
16
D2(D
)
D
15
D3(D
)
E
14
D4(D
)
I
13
D5(D
)
F
12
D6(D
)
G
11
D7(D
)
H
21
CKW
CLOCK
23
ENA
GENERATOR
24
ENN
7
MODE
TEST
5
BISTEN
LOGIC
25
FOTO
HDSP-2111 (HP)
8-COLUMN DISPLAY (5x7-DOT) WITH DECODER AND DRIVER
—TOP VIEW—
28 27 26 25 24 23
20 19 18 17 16 15
1 2 3 4 5 6 7 8 9 10 11 12 13 14
PIN
PIN
I/O
SIGNAL
I/O
NO.
NO.
RST
1
I
15
—
FL
2
I
16
—
3
I
A0
17
I
4
I
A1
18
I
5
I
A2
19
I
6
I
A3
20
I
7
I
STR
21
—
8
I
STR
22
—
9
I
STR
23
I
10
I
A4
24
I
CLS
11
I
25
I
12
I
CK
26
I
WR
13
I
27
I
14
—
V
28
I
DD
3-4
18
26
D0(D
)
OUT A_
B
17
27
D1(D
)
C
OUT A+
16
25
D2(D
)
D
15
1
D3(D
)
OUT B_
E
24
14
28
D4(D
)
OUT B+
I
13
23
D5(D
)
F
12
2
D6(D
)
G
OUT C_
22
11
3
D7(D
)
OUT C+
H
21
10
8
SVS(D
)
J
RP
20
19
SC/D(D
)
A
5
19
BISTEN
7
MODE
21
CKW
23
ENA
24
ENN
25
FOTO
SIGNAL
D3(D
)
E
INPUTS
D2(D
)
D
BISTEN
: BUILT-IN SELF TEST ENABLE
D1(D
)
C
CKW
: CLOCK WRITE
D0(D
)
B
D0 - D7
: PARALLEL DATA
SC/D(D
)
A
ENA
: ENABLE PARALLEL DATA
GND
ENN
: ENABLE NEXT PARALLEL DATA
CKW
FOTO
: FIBER OPTICAL TRANSMITTER OFF
V
DD
MODE
: ENCODER MODE SELECT
ENA
SC/D (D
A
)
: SPECIAL CHARACTER/DATA SELECT
ENN
SVS (D
)
: SEND VIOLATION SYMBOL
J
FOTO
OUT A_
OUTPUTS
OUT A+
OUT A+, OUT A_
: DIFFERENTIAL SERIAL DATA
OUT B+
OUT B+, OUT B_
: DIFFERENTIAL SERIAL DATA
OUT C+, OUT C_
: DIFFERENTIAL SERIAL DATA
RP
: READ PULSE
ENABLE
INPUT
REGISTER
27
ENCODER
OUT A+
26
OUT A_
28
OUT B+
SHIFTER
1
OUT B_
3
OUT C+
2
OUT C_
8
RP
INPUTS
RST
A0 - A4
: ADDRESS
CK
CE
: CHIP ENABLE
CLS
CK
: CLOCK
CLS
: CLOCK SELECT
D0 - D7
: DATA
FL
: FLASH RAM
RD
: READ
D7
RST
: RESET
STR
: SUBSTR BIAS
WR
: WRITE
D6
SIGNAL
D5
D4
GND
D3
GND
CE
D2
D1
RD
D0
D0
D1
—
—
D2
D3
D4
D5
D6
D7
CY7B933-JC (CYPRESS)
RECEIVER
—TOP VIEW—
5
6
7
8
9
10
11
PIN
I/O
SIGNAL
NO.
1
I
INA_
2
I
INA+
B
3
I
A/
BISTEN
4
I
5
I
RF
6
—
GND
RDY
7
O
8
—
GND
9
—
V
CC
10
O
RVS(Q
)
J
11
O
Q7(Q
)
H
12
O
Q6(Q
)
G
13
O
Q5(Q
)
F
14
O
Q4(Q
)
I
5
RF
3
B
A/
2
INA+
1
INA_
28
INB(INB+)
27
SI(INB_)
PECL
23
TTL
SO
25
REFCLK
7
TEST
MODE
4
BISTEN
LOGIC
1
12
÷32
÷7
÷128
OSC
11
MUX RATE
RAM READ LOGIC
28
PAGE RAM
CONTROL
27
WORD
26
DECODE
USER RAM
LOGIC
25
MEMORY
24
ASCII
(8 x BITS)
23
CODE
(7 BITS)
20
19
FLASH RAM
(8 x BITS)
ADDRESS DECODER
3
4
5
6
10 13
17 18
2
WR CE RD FL
A0 A1 A2 A3 A4
INPUTS
B
A/
: SERIAL DATA INPUT SELECT
BISTEN
: BUILT-IN SELF-TEST ENABLE
25
INA+, INA_
: SERIAL DATA A
24
INB+, INB_
: SERIAL DATA B
23
MODE
: DECODER MODE SELECT
22
REFCLK
: REFERENCE CHECK
21
RF
: REFRAME ENABLE
20
SI
: STATUS
19
OUTPUTS
CKR
: CLOCK READ
Q0(Q
)-Q7(Q
)
: PARALLEL DATA
B
H
RDY
: DATA OUTPUT READY
RVS(Q
)
: RECEIVED VIOLATION SYMBOL
J
D
SC/
(Q
)
: SPECIAL CHARACTER/DATA SELECT
A
SO
: STATUS
PIN
I/O
SIGNAL
NO.
15
O
Q3(Q
)
E
16
O
Q2(Q
)
D
17
O
Q1(Q
)
C
18
O
Q0(Q
)
B
D
19
O
SC/
(Q
)
A
20
—
GND
V
21
—
CC
22
O
CKR
23
O
SO
24
—
V
CC
25
I
REFCLK
26
I
MODE
27
I
SI(INB_)
28
I
SI(INB+)
FRAMER
DATA
SHIFTER
DECODER
REGISTER
CLOCK
DECODER
SYNC
OUTPUT
REGISTER
22
7
10 - 18
19
RDY
D
CKR
Q0 - Q7
SC/
(Q
- Q
)
(Q
)
B
H
A
ROW CONTROL LOGIC
AND
ROW DRIVERS
0
1
BLINK RATE
TIMING AND CONTROL LOGIC
ROW DECODER
ROM
RAM
COLUMN
128 x 7 BITS
16 x 7 BITS
DATA
ASCII
USER'S
CHARACTER
CHARACTER
DECODER
DECODER
(4.48 K BITS)
(4.48 K BITS)
DISPLAY
2
3
4
5
6
7
MAIN
COLUMN
SUB
DRIVERS
LATCHES
FOR
DIGIT
DIGIT
0 TO 7
0 TO 7
BDX-N1000
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