Sony BDX-N1000 Maintenance Manual page 51

IC
78P7200-IH (TDK SEMI)
DS3/E3/STS-1 LINE INTERFACE WITH RECEIVE EQUALIZER
—TOP VIEW—
5 25
6 24
7 23
8 22
9 21
10 20
11 19
PIN PIN
I/O SIGNAL I/O SIGNAL
NO. NO.
1
I LIN+ 15 I TNEG
2 — NC 16 TCLK
I
3 I LIN_ 17 — V
CC
OPT2
4
— NC 18 I
5 I RFO 19 I LF1
6
— GND 20 I LF2
7 — V 21 — NC
CC
8
— GND 22 — GND
9 O LOUT+ RCLK
23 O
10 — NC 24 O RNEG
11
O LOUT_ 25 O RPOS
12 I LBO 26 — V
CC
OPT1 LOWSIG
13
I 27 O
14 I TPOS 28 I CPD
19
LF1
20
LF2
28
CPD
5
RFO
LOW-LEVEL SIGNAL
27
LOWSIG
DETECTION
1
LIN+ SIGNAL
EQ.
3
ACQUISITION
LIN_
16
TCLK
PULSE
PULSE
14
TPOS
GENERATOR
SHAPER
15
TNEG
13
OPT1
18
OPT2
12
LBO
CLC014AJE-TR (NS)
ADAPTIVE CABLE EQUALIZER FOR HIGH-SPEED DATA RECOVERY
—TOP VIEW—
8
DI
DO
V 1 14
CC
9
DI
12
MUTE
V 2 13 DO
CC
6
AEC+
MUTE
OEM 3 12
7
AEC_
V 4 11 GND
CC
CD 5 10 GND
DI
AEC+ 6 9
AEC_ 7 8 DI
INPUTS
AEC+ : ADAPTIVE EQUALIZER CAPACITOR (POSITIVE)
AEC_ : ADAPTIVE EQUALIZER CAPACITOR (NEGATIVE)
DI
DI, : DATA
MUTE
: MUTING
OUTPUTS
CD : CARRIER DETECT
DO
DO, : DATA
OEM : OUTPUT EYE MONITOR
OEM BUFFER
8
DI QUANTIZED
EQUALIZER
9
DI FB COMPARATOR
12
MUTE
ADAPTIVE
SERVO CONTROL
6 7
AEC+ AEC_
BDX-N1000
INPUTS
CPD : EXTERNAL CAPACITOR
LBO : TRANSMITTER LINE BUILDOUT
CONTROL
LF1, LF2 : FILTER NETWORK
LIN+, LIN_ : DIFFERENTIAL SIGNAL
OPT1 OPT2
, : TRANSMIT OPTION 1, 2
RFO : EXTERNAL REGISTER
TCLK : TRANSMITTER CLOCK
TNEG : TRANSMITTER NEGATIVE DATA
TPOS : TRANSMITTER POSITIVE DATA
OUTPUTS
LOUT+ : POSITIVE DATA PULSE
LOUT_ : NEGATIVE DATA PULSE
LOWSIG
: LOW SIGNAL
RCLK : RECOVERED CLOCK
RNEG : RECEIVER NEGATIVE PULSE
RPOS : RECEIVER POSITIVE PULSE
OTHER
NC : NO CONNECT
CLOCK
23
RCLK
RECOVERY
25
DATA RPOS
24
DETECTION
RNEG
OUTPUT
9
DRIVER, LOUT+
11
LINE
LOUT_
BUILDOUT
13
DO
14
DO
3
OEM
5
CD
3
OEM
13
DO
14
DO
5
CD
CAS9053 (COMATLAS)
AAL1 VIDEO ERROR PROCESSOR
—TOP VIEW—
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
PIN PIN PIN
I/O SIGNAL I/O SIGNAL
NO. NO. NO.
1 I/O DUP3 18 — GND 35
2 — V 19 I MODE 36
CC
ENR
3 — GND 20 O 37
4 — GND 21 I TCK 38
RESET
5 I/O DUP4 22 I 39
6 I/O DUP5 23 — GND 40
7 I/O DUP6 24 I NOR4 41
8 I/O DUP7 25 I NOR3 42
9 — V 26 I NOR2 43
CC
10 I ADR2 27 I NOR1 44
11 I ADR1 28 I NOR0 45
12 I ADR0 29 — GND 46
13 I TRST 30 I DIN7 47
14 I TMS 31 I DIN6 48
15 I TDI 32 I DIN5 49
16 — RESERVED 33 I DIN4 50
17 — GND 34 — GND 51
RECEPTION ( MODE = 0 )
30 - 33,
8
40 - 43
8
DELAY LINE
DIN7 - DIN0
44
SCOR
SN AND SNP
COMPUTATION,
FIFO
45 DEINTERLEAVING
ENNOR
SYNCHRO
AND
24 - 28
5
NOR4 - NOR0
SUPERVISION
35
CLK
22
RESET
8
66 - 68,
1, 5 - 8
8
DUP0 - DUP7
8
10 - 12 3
ADR2 - ADR0
62
8
CSEL
65
WR
64
RD
TRANSMISSION ( MODE = 1 )
30 - 33,
8
40 - 43
8
DIN7 - DIN0
REED-SOLOMON
20
ENR
ENCODER
(128,124)
44
F
35
CLK
22
RESET
66 - 68,
1, 5 - 8
8
DUP0 - DUP7
10 - 12 3
ADR2 - ADR0
8
62
CSEL
AUTOTEST
65
8
WR
64
RD
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
PIN
I/O SIGNAL I/O SIGNAL
NO.
I CLK 52 — V
CC
— V 53 — GND
CC
— V 54 O DOUT4
CC
— GND 55 O DOUT5
— GND 56 O DOUT6
I DIN3 57 O DOUT7
MATSTART
I DIN2 58 O
UNCORR
I DIN1 59 O
FUS
I DIN0 60 O
SCOR FTOT
I /F 61 O
ENNOR CSEL
I 62 I
O TDO 63 — V
CC
RD
O DOUT0 64 I
WR
O DOUT1 65 I
O DOUT2 66 I/O DUP0
O DOUT3 67 I/O DUP1
— V 68 I/O DUP2
CC
8
DEINTERLEAVING
MATRICES
8
47 - 50,
8
54 - 57
DOUT0 -DOUT7
REED-SOLOMON
61
FTOT
DECODER
8
60
FUS
(128,124)
8
59
UNCORR
WITH ERASURES
58
MONITORING MATSTART
8
INTERLEAVING
MATRICES
8 8
8
47 - 50,
8
54 - 57
DOUT0 -DOUT7
SAR-PDU 61
FTOT
HEADER
60
FUS
ADDER
58
MATSTART
IC
3-3