Sony SIU-100 Service Manual page 120

1
001,002,003,007,008,009,011,013
2
3
4
5
A B
CPU_BUS
+5V
R505
680
IC500
2 RN5VD42AA-TL
TP500
VDD
R506
10k
5 1
CD OUT
GND
3
C500
1uF
CPUPLD_TDI
GND
+3.3V
IC501
RN5VD30AA-TL
2
S500
VDD
1 2 5 1
CD OUT
3 4
GND
GND C504
5 0.1uF
3
C501
1uF
GND
V_SYNC_IN
TMS
011,012,013 TCK
+5V +3.3V
C502
0.1uF
RB500 RB501
1k 1k
GND IC502
20
SN74LVC541APWR
2 Vcc 18
XPWR0+5_ALM
A1 Y1
3 17
XPWR0+3_ALM
A2 Y2
4 16
XPWR0+15_ALM
A3 Y3
5 15
XPWR0-15_ALM
A4 Y4
6 14
XPWR1+5_ALM
A5 Y5
7 13
XPWR1+3_ALM
A6 Y6
8 12
XPWR1+15_ALM
A7 Y7
9 11
XPWR1-15_ALM
A8 Y8
1
G1
19
G2
GND
10
GND
C
CPU-353 (5/14) CPU-353 (5/14)
+3.3V
C508 C510
C505
0.1uF 0.1uF
100uF
10V
XRES
1
GND1
2
TDI
3
A[0]
IO8/B7
4
A[1]
IO9/B6
5
A[2]
IO10/B5
6
A[3]
IO11/B4
7
A[4]
IO12/B3
8
A[5]
IO13/B2
9
A[6]
IO14/B1
10
A[7]
IO15/B0
11
CKIO_0
I0/CLK0
12
VCC1
13
GND2
14
I1/CLK1
15
A[8]
IO16/C0
16
A[9]
IO17/C1
17
A[10]
IO18/C2
18
A[11]
IO19/C3
19
A[12]
IO20/C4
20
A[13]
IO21/C5
21
A[14]
IO22/C6
22
A[15]
IO23/C7
23
TMS
24
TCK
25
GND3
C507
0.1uF
C509
0.1uF
GND
D500
CL-191HR-CD-T
D501
CL-191YG-CD-T
D502
CL-191YG-CD-T
R500
+3.3V
D503
220
CL-191YG-CD-T
R501
220
R502
220
R503
+3.3V
220
RB504
+3.3V +3.3V
1k
C506 C514
0.1uF 0.1uF
GND
20 16
GND
3 VCC 2 1 VCC 15
BD[0] BD[0]
1D 1Q A Y0
4 5 2 14
BD[1] BD[1]
2D 2Q B Y1
7 6 3 13
BD[2] BD[2]
3D 3Q C Y2
8 9 12
BD[3] BD[3]
4D 4Q Y3
13 12 6 11
BD[4] BD[4]
5D 5Q G1 Y4
14 15 4 10
BD[5] BD[5]
6D 6Q G2A Y5
9
17 16 5
BD[6] BD[6]
7D 7Q G2B Y6
18 19 7
BD[7] BD[7]
8D 8Q Y7
11 GND
XSLOTWR
CLK
1 8
OE
GND
10
GND GND
XPOWER_CS
IC507
IC504
XBRD
SN74LVC138APWR-12
SN74LVC374APWR
7-10 7-10
D E
JTAG_BUS
IC503
M4A3-128/64-10VC-CPUV001
75
GND12
74
CPUPLD_TDO
TDO
73 RB502
TRST 22
72
1 2 XIRL[3]
IO55/G7
71
3 4 XIRL[2]
IO54/G6
70
5 6 XIRL[1]
IO53/G5
69
7 8 XIRL[0]
IO52/G4
68
XNMI
IO51/G3
67
XPOWER_CS
IO50/G2
66
XFPGACS[1]
IO49/G1
65
XFPGACS[0]
IO48/G0
C513 +3.3V
64
XWE[3]
I4/CLK3 0.1uF
63
GND11
62 R508
VCC4 10k
61
XEINT
I3/CLK2
60
XFPGAWR
IO47/F0
59
XSLOTWR
IO46/F1
R507
58
XCKCS
IO45/F2 10k
57
XEINTCP
IO44/F3
56
XECPCS
R510
IO43/F4
100
55
XEMUTE
IO42/F5
54
XEPD
IO41/F6
53
XERESET
IO40/F7
52
ENABLE
51
GND10
R509
100
ISA_BUS
FPGA_CONF
+3.3V
C511
0.1uF
GND
20
3 VCC 2
BD[0] FD[0]
1D 1Q
4 5
BD[1] FD[1]
8
2D 2Q
BD[2] 7 6 FD[2]
3D 3Q 6
8 9
BD[3] FD[3]
4
4D 4Q
13 12
BD[4] FD[4]
5D 5Q 2
2
14 15
BD[5] FD[5]
6D 6Q
4
17 16
BD[6] FD[6]
7D
7Q 6
18 19
BD[7] FD[7]
8D 8Q
8
11
XFPGAWR
CLK
1 IC505
OE
SN74LVC374APWR
GND
RB503
10
+3.3V
1k
C515
0.1uF
GND
GND
20 RB508
100
2 Vcc 18
1 2 SLOTSEL[0]
A1 Y1
3 17 3 4 SLOTSEL[1]
A2 Y2
4 16 SLOTSEL[2]
5 6
A3 Y3
5 15 SLOTSEL[3]
7 8
A4 Y4
6 14
1 2 SLOTSEL[4]
A5 Y5
7 13 SLOTSEL[5]
3 4
A6 Y6
SLOTSEL[6]
8 12 5 6
A7 Y7
9 11 SLOTSEL[7]
7 8
A8 Y8
1
OE1
RB509
19
OE2
100
GND
10
GND
IC506
SN74LVC540APWR
F G
013
009,010
001,007
+3.3V
7
RB506
10k
5
3
1
1
3
5 10k
RB507
7
CPU-353 (5/14)
BOARD NO. 1-686-477-11, 12
SIU-100/100T
SIU-100_CPU-353_003_5
SIU-100/100T
H