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SAL-1001 BOARD SCHEMATIC (14 OF 28)
1
A
B
C
D
E
F
2014/03/31 15:05
[ SOC ]
240
IC9000
CXD4741GB
2014/03/31 15:05
[ JIG ]
YES
D6301
SML-310MTT86
R6319
510
1/16W
CHIP
2014/03/31 15:05
G
[
]
C6305
0.022
25V
X7R
CN6301
15P
BLK
CN6302
7P
L6301
90ohm
L6302
90ohm
L6303
0uH
L6304
90ohm
L6305
90ohm
R6320
0
CHIP
R6321
0
CHIP
H
R6323
0
CHIP
R6324
0
CHIP
R6325
0
CHIP
R6347
0
CHIP
FMP-X10
2
3
4
X_SYSTEM_RST
20_3K/4_3D/9_8J/24_2H/17_4B/17_4F/17_11B/40_2C/40_7C
ETHER
X_ETHER_PHY/WIFI_RST
5_7D/5_15F/40_10F
(from STBY_GPIO_14)
X_ETHER_WAKE
9_10J/5_2H
(to STBY_GPIO_15)
RMII I/F
ETHERNET RMII
1
RMII_TX_EN
R6329
XX
1
RMII_TXD_1
AN6
R6330
XX
ETHER_TX_EN
1
AM7
R6331
XX
RMII_TXD_0
ETHER_TXD_0
AP6
ETHER_TXD_1
1
AN5
R6332
XX
RMII_CRS_DV
ETHER_CRS_DV
1
RMII_RXD_0
AP7
R6333
XX
ETHER_RXD_0
1
RMII_RXD_1
AN7
R6334
XX
ETHER_RXD_1
ETH_MDC
AM6
R6339
47
ETHER_MDCK
AP5
R6340
47
ETH_MDIO
ETHER_MDIO
1
AP4
R6335
XX
ETH_REFCLK
ETHER_REFCLK
*IC9000
CXD4741GB
Crystal
Device
R6327
0
CH
50V
8p
C6301
1
R6328
0
X6301
25MHz
2
CH
50V
8p
C6302
NDK3225
GND_D
0
R6306
ETH_REFCLK
47
240AVS
CXD4741GB-1
NO
XX
XX
Type_A_SHISAKU
Type_A_MP
Type_B_SHISAKU
Type_B_MP
0.022
0.022
XX
XX
25V
25V
X7R
X7R
XX
XX
15P
15P
BLK
BLK
7P
7P
XX
XX
XX
XX
90ohm
90ohm
90ohm
90ohm
XX
XX
XX
XX
0uH
0uH
XX
XX
90ohm
90ohm
90ohm
90ohm
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
0
0
CHIP
CHIP
XX
XX
0
0
CHIP
CHIP
XX
XX
0
0
CHIP
CHIP
XX
XX
0
0
CHIP
CHIP
5
6
7
WOL Standby
X_SYSTEM_RST
S20
X_ETHER_PHY/WIFI_RST
10/14
R6348
XX
R6308
0
STB3.3V_AY
+3.3V_MAIN
WOL Standby
STBY_+3.3V -> +3.3V_MAIN
S20
STBY3.3V_AY
1
LED A
LED1_PHYAD1
*R6319
XX
*D6301
XX
1
1
1
GND_D
18
17
16
15
14
13
19
LED1/PHYAD[1]
TXD[0]
12
CL6302
20
CRS/CRS_DV
REF_CLK
11
CL6301
IC6301
21
RXER/FXEN
DVDD33
10
RTL8201FR-VB-CGT
R6345
47
RMII_RXD_1
22
DVDD10OUT
RXD[1]
9
R6346
47
RMII_RXD_0
23
CKXTAL1
RXD[0]/CLK_CTL
8
4 2
C
X K
A T
2 L
AVDD33
7
1
2
3
4
5
6
C6303
C6308
C6309
C6310
R6311
0.1
0.1
0.1
XX
2.49k
16V
1/16W
16V
16V
AY_ET_RN
X7R
X7R
X7R
1%
1005
1005
1005
AY_ET_RP
C6307
0.1
16V
X7R
GND_D
1005
AY_ET_TN
AY_ET_TP
Rx :
100
*R6324
*R6323
0
0
Tx :
100
*R6325
*R6347
0
0
CN6301
+5.0V_REAR_USB
4H
HUB3_USB1_CN1_M
JL6503
4H
HUB3_USB1_CN1_P
JL6504
JL6501
GND_D
VD6503
VD6502
XX
XX
SECTION 4 - DIAGRAMS
8
9
10
[PHY Strap settings]
LED0/PHYAD[0]/PMEB/INTB (18pin)
0 : PHYAD[0] = LED0 = 0
1 : PHYAD[0] = LED0 = 1 (default)
*An external PU is necessary in WOL mode.
LED1/PHYAD[1] (19pin)
0 : PHYAD[1] = LED1 = 0 (default)
1 : PHYAD[1] = LED1 = 1
RXD[0]/CLK_CTL (8pin : internal PD)
0 : REFCLK output mode (default)
1 : REFCLK input mode
RXD[1] (9pin : internal PD)
0 : 18pin supports LED function.(default)
1 : 18pin supports WOL/INT function.
RXER/FXEN (21pin : internal PD)
0 : UTP mode (default)
1 : Fiber mode
CN6302
-A
-
No.14
*L6302
90ohm
GND
Type A
Rx(-)
FOR INSTALL
Rx(+)
Tx(-)
*L6305
90ohm
Tx(+)
*C6305
0.022
*CN6302
19
18
17
16
1005
X7R
16V
0.1
C6304
*L6301
90ohm
1
4
5
2
3
Type B
11
10
*L6304
90ohm
9
ETHER
1
4
8
2
3
7
6
12
JL6502
1
13
14
*L6303
0uH
15
1
*CN6301
15P
BLK
Pattern Short
1
USB1-REAR(HDD)
R6301
R6329,R6330,R6331,R6332,R6333,
R6334,R6335,R6336,R6337,R6338
R6320,R6321
REF
GND_D
ORIGINAL
SAL BOARD
MODEL
DESCRIPTION
AY ETHER
PART NO.
Proto
ALL resistors are in ohms,W unless otherwise noted.
ALL capacitors are in uF(p:pF)unless otherwise noted.
11
SHEET
15/29
50
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