System Synchronization Clock (Pxi_Clk10, Pxie_Clk100, Pxie_Sync100) Specifications; 10 Mhz System Reference Clock: Pxi_Clk10; 100 Mhz System Reference Clock: Pxie_Clk100 And; Pxie_Sync100 - National Instruments NI PXIe-1082 Installation Manual

System Synchronization Clock (PXI_CLK10, PXIe_CLK100,
PXIe_SYNC100) Specifications
Note For other specifications, refer to the PXI-1 Hardware Specification.
For other specifications, refer to the PXI-5 PXI Express Hardware Specification.
Note
8-Slot NI PXIe-1082 Backplane Installation Guide

10 MHz System Reference Clock: PXI_CLK10

Maximum slot-to-slot skew ....................500 ps
Accuracy .................................................±25 ppm max (guaranteed over
Maximum jitter .......................................5 ps RMS phase-jitter (10 Hz to
Duty-factor..............................................45% to 55%
Unloaded signal swing............................3.3 V ±0.3 V

100 MHz System Reference Clock: PXIe_CLK100 and

PXIe_SYNC100

Maximum slot-to-slot skew ....................100 ps
Accuracy .................................................±25 ppm max (guaranteed over
Maximum jitter .......................................3 ps RMS phase-jitter (10 Hz to
Duty-factor for PXIe_CLK100...............45% to 55%
Absolute single-ended voltage swing
(When each line in the differential pair
has 50 Ω termination to 1.30 V
or Thévenin equivalent)..........................400 to 1000 mV
External 10 MHz Reference Out (on J36)
Accuracy .................................................±25 ppm max (guaranteed over
Maximum jitter .......................................5 ps RMS phase-jitter (10 Hz to
the operating temperature range)
1 MHz range)
the operating temperature range)
12 kHz range)
2 ps RMS phase-jitter (12 kHz to
20 MHz range)
the operating temperature range)
1 MHz range)
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