Denon RCD-N9 Service Manual page 75

Part Number
EN5339QI
EVB-EN5339QI
Packing and Marking
Pin Assignments (Top View)
EN5339QI (NETWORK : IC63, IC64, IC65, IC66)
NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage.
However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.
NOTE B: Grey area highlights exposed metal on the bottom of the package that is not to be mechanically or electrically
connected to the PCB. There should be no traces on PCB top layer under these keep out areas.
NOTE C: White 'dot' on top left is pin 1 indicator on top of the device package.
Pin Description
EN5339QI Pin Discriptions
PIN NAME
NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage.
However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.
NOTE B: Grey area highlights exposed metal on the bottom of the package that is not to be mechanically or electrically
1, 21-24 NC(SW)
connected to the PCB. There should be no traces on PCB top layer under these keep out areas.
NOTE C: White 'dot' on top left is pin 1 indicator on top of the device package.
Pin Description
2-3, 8-9 PGND
PIN
4-7 VOUT
1, 21-24
10 TST2
11 TST1
PIN NAME
2-3, 8-9
12 TST0
4-7
06903
13 NC
10
11
06903
14 VFB
15 AGND
16 AVIN
17 POK
18 ENABLE
19-20 PVIN
25,26 PGND
Functional Block Diagram
EN5339QI Block Diagram
Functional Description
Overview
The EN5339QI is a highly integrated synchronous
buck converter with an internal inductor utilizing
advanced CMOS technology to provide high
switching frequency, while also maintaining high
efficiency. The EN5339QI is a high power density
device packaged in a tiny 4x6x1.1mm 24-pin QFN
package. Its high switching frequency allows for the
Package Markings Temp Rating (°C)
EN5339 -40 to +85
2
PGND 25
EN5339
PGND
Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
PGND 3
Keep-Out
4
VOUT
5 6 7
24 23 22
1
NC(SW)
PGND 2
25
Figure 3: Pin Out Diagram (Top View) PGND
PGND
3
Keep-Out
4
VOUT
5 6 7
Figure 3: Pin Out Diagram (Top View)
FUNCTION
NO CONNECT: These pins are internally connected to the common switching node of the
internal MOSFETs. They must be soldered to PCB but not be electrically connected to any
external signal, ground, or voltage. Failure to follow this guideline may result in device
damage.
Input and output power ground. Connect these pins to the ground electrode of the input and
output filter capacitors. See VOUT, PVIN descriptions and Layout Recommendation for more
NAME FUNCTION
details.
NO CONNECT: These pins are internally connected to the common switching node of the
Regulated converter output. Connect to the load and place output filter capacitor(s) between
internal MOSFETs. They must be soldered to PCB but not be electrically connected to any
NC(SW)
these pins and PGND pins 8 and 9. See layout recommendation for details
external signal, ground, or voltage. Failure to follow this guideline may result in device
damage.
Test Pin. For Altera internal use only. Connect to AVIN at all times.
Input and output power ground. Connect these pins to the ground electrode of the input and
Test Pin. For Altera internal use only. Connect to AVIN at all times.
FUNCTION
PGND output filter capacitors. See VOUT, PVIN descriptions and Layout Recommendation for more
details.
Test Pin. For Altera internal use only. Connect to AVIN at all times.
Regulated converter output. Connect to the load and place output filter capacitor(s) between
VOUT
NO CONNECT: This pin must be soldered to PCB but not electrically connected to any other
these pins and PGND pins 8 and 9. See layout recommendation for details
July 9, 2014
pin or to any external signal, voltage, or ground. This pin may be connected internally. Failure
TST2 Test Pin. For Altera internal use only. Connect to AVIN at all times.
TST1 Test Pin. For Altera internal use only. Connect to AVIN at all times.
to follow this guideline may result in device damage.
This is the external feedback input pin. A resistor divider connects from the output to AGND.
The mid-point of the resistor divider is connected to VFB. A feed-forward capacitor is
required parallel to the upper feedback resistor (R
on the VFB node voltage equal to 0.600V.
The quiet ground for the control circuits. Connect to the ground plane with a via right next to
the pin.
Analog input voltage for the control circuits. Connect this pin to the input power supply (PVIN)
at a quiet point. Decouple with a 1uF capacitor to AGND.
POK is an open drain output. Refer to Power OK section for details. Leave POK open if
unused.
Output Enable. A logic high level on this pin enables the output and initiates a soft-start. A
logic low signal disables the output and discharges the output to GND. This pin must not be
left floating.
Input power supply. Connect to input power supply and place input filter capacitor(s) between
these pins and PGND pins 2 to 3.
Not a perimeter pin. Device thermal pad to be connected to the system GND plane for heat-
sinking purposes. See Layout Recommendation section.
UVLO
Thermal Limit
Current Limit
ENABLE
Soft Start
(-)
PWM
Comp
(+)
Sawtooth
Generator
TST
AVIN
Figure 4: Functional Block Diagram
Package Description
24-pin (4mm x 6mm x 1.1mm) QFN T&R
15
QFN Evaluation Board
26
14
PGND
13
8 9 10 11 12
20 19 18
21 17
Keep-Out
16 AVIN
15 AGND
26
14
VFB
PGND
13
NC
8 9 10 11 12
www.altera.com/enpirion, Page 2
www.altera.com/enpirion, Page 2
July 9, 2014
). The output voltage regulation is based
A
POK PVIN
POK
P-Drive
Logic
N-Drive
Compensation
Network
(-)
Error
Amp
(+)
DAC
VREF
BIAS
Package Boundary
AGND
Stability and Compensation
The EN5339QI utilizes an internal compensation
network that is designed to provide stable operation
over a wide range of operating conditions. The
75
output compensation circuit may be customized to
improve transient performance or reduce output
voltage ripple with dynamic loads.
Soft-Start
AGND
VFB
NC
EN5339QI
Rev D
Rev D
EN5339QI
NC
(SW)
VOUT
PGND
VFB