Denon RCD-N9 Service Manual page 73

SLES273A – APRIL 2013 – REVISED JUNE 2013
2
2.1
2.1.1 TAS5558 Pin Assignments
TAS5558 (MAIN : IC23)
www.ti.com
TAS5558 Pin Discriptions
2.1.2 Pin Descriptions
PIN
NAME
ASEL_EMO2
AVDD
AVDD_PWM
AVSS
AVSS_PWM
4
BKND_ERR
DVDD1
DVDD2
DVSS1
DVSS2
EMO1
HP_SEL
LRCLK
LRCLKO /
LRCKIN_2
MLCK
MUTE
OSCRES
PDN
PLL_FLTM
PLL_FLTP
PSVC/MCLKO
PWM_HPM_L
PWM_HPM_R
PWM_HPP_L
PWM_HPP_R
PWM_M_1
PWM_M_2
PWM_M_3
PWM_M_4
PWM_M_5
PWM_M_6
PWM_M_7
PWM_M_8
PWM_P_1
(1) Type: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
(2) All pullups are 20-μA weak pullups and all pulldowns are 20-μA weak pulldowns. The pullups and pulldowns are included to ensure
proper input logic levels if the terminals are left unconnected (pullups → logic-1 input; pulldowns → logic-0 input). Devices that drive
inputs with pullups must be able to sink 20 μA while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be
able to source 20 μA while maintaining a logic-1 drive level.
Copyright © 2013, Texas Instruments Incorporated
Device Information
Physical Characteristics
PWM_HPM_L
1
PWM_HPP_L
2
PWM_HPM_R
3
PWM_HPP_R 4
AVSS 5
PLL_FLTM
6
PLL_FLTP
7
VR_ANA
8
AVDD 9
ASEL_EMO2 10
MCLK 11
OSCRES
12
DVSS2_CORE
13
DVDD2_CORE 14
EMO1 15
RESET 16
HP_SEL
17
PDN
18
MUTE 19
SDA 20
SCL 21
LRCLK
22
SCLK
23
SDIN1
24
SDIN2
25
SDIN2_1 26
SDIN2_2
27
VR_DIG
28
Figure 2-1. TAS5558 Pinout
5-V
(1)
TYPE TERMINATION
TOLERANT
NO.
10 DIO Pullup
9 P
50 P
5 P
51 P
Device Information
34 DI Pullup
Submit Documentation Feedback
Product Folder Links:
35 P
14 P
36 P
13 P
15 DO
17 DI 5 V Pullup
22 DI 5 V Pulldown
31 DIO 5V Pulldown
11 DI
19 DI 5 V Pullup
12 DO 1MΩ Resistor
18 DI 5 V Pullup
6 AIO
7 AIO
33 DO
1 DO
3 DO
2 DO
4 DO
38 DO
40 DO
42 DO
44 DO
53 DO
55 DO
46 DO
48 DO
39 DO
Submit Documentation Feedback
Product Folder Links:
DCA Package
(Top View)
PWM_P_6
56
PWM_M_6
55
PWM_P_5
54
PWM_M_5
53
VR_PWM
52
AVSS_PWM
51
AVDD_PWM
50
PWM_P_8
49
PWM_M_8
48
PWM_P_7
47
PWM_M_7
46
PWM_P_4
45
PWM_M_4
44
PWM_P_3
43
TAS5558
PWM_M_3
42
PWM_P_2
41
PWM_M_2
40
PWM_P_1
39
PWM_M_1
38
VALID
37
DVSS1_CORE
36
DVDD1_CORE
35
BKND_ERR
34
33 PSVC/MLCK
32 TEST
LRCLKO (LRCK_2)
31
30 SCLKO (SCLK_2)
SDOUT (SDIN5)
29
P0113-02
SLES273A – APRIL 2013 – REVISED JUNE 2013
(2)
DESCRIPTION
I2C Address Select. Address will 0X34/0X36 with the value of pin being "0' or
"1" during de-assertion of reset. Can be programmed to be an output (as energy
manager output for subwoofer)
Analog supply (3.3 V) for PLL.
3.3-V analog power supply for PWM. This terminal can be connected to the
same power source used to drive power terminal DVDD; but to achieve low PLL
jitter, this terminal should be bypassed to AVSS_PWM with a 0.1-μF low-ESR
capacitor.
Analog ground
Analog ground for PWM. Must have direct return Cu path to analog 3.3V supply
for optimized performance.
Copyright © 2013, Texas Instruments Incorporated
Active-low. A back-end error sequence is generated by applying logic low to this
terminal. The BKND_ERR results in no change to I2C parameters, with all H-
TAS5558
bridge drive signals going to a hard-mute state (Non PWM Switching).
3.3-V digital power supply. (It is recommended that decoupling capacitors of
0.1 μF and 10 μF be mounted close to this pin).
3.3-V digital power supply for PWM. (It is recommended that decoupling
capacitors of 0.1 μF and 10 μF be mounted close to this pin).
Digital ground 1
Digital ground 2
Energy Manger Output interrupt - Asserted high when threshold is exceeded.
Headphone/speaker selector. When a logic low is applied, the headphone is
selected (speakers are off). When a logic high is applied, speakers are selected
(headphone is off).
Serial-audio data left/right clock (sampling-rate clock)
LRCLK for I2S OUT. Can also be used as LRCKIN_2 (I2S Input for SDIN2_x
and SRC Bank 2)
3.3-V master clock input. The input frequency of this clock can range from 2
MHz to 50 MHz.
Soft mute of outputs, active-low (muted signal = a logic low, normal operation =
a logic high). The mute control provides a noiseless volume ramp to silence.
Releasing mute provides a noiseless ramp to previous volume.
Oscillator resistor (1% tolerance).
Power down, active-low. PDN powers down all logic and stops all clocks
whenever a logic low is applied. The I2C parameters are preserved through a
power-down cycle, as long as RESET is not active.
PLL negative filter.
PLL positive filter.
Power-supply volume control PWM output or MCKO for external ADC (SDIN5
Source)
PWM left-channel headphone (differential –)
PWM right-channel headphone (differential –)
PWM left-channel headphone (differential +)
PWM right-channel headphone (differential +)
PWM 1 output (differential –)
PWM 2 output (differential –)
PWM 3 output (differential –)
PWM 4 output (differential –)
PWM 5 output (lineout L) (differential –)
PWM 6 output (lineout R) (differential –)
PWM 7 output (differential –)
PWM 8 output (differential –)
PWM 1 output (differential +)
TAS5558
73
www.ti.com
TAS5558
Device Information 5