Analog Signal Paths; Successive Approximation - Alesis MidiVerb 3 Service Manual

3.0 ANALOG SIGNAL PATHS

The inputs (stereo) from J1 and J2 pass through the small toroids for RF suppression
(bypassed in some units), A.C. coupled (C1, C2) and have their impedances fixed at 1M by R2 and
R3. While operating the unit monauraly, the input impedance fixed at 500K (R2, and R3, in parallel).
From there, the inputs are buffered by U1, and passed through the input potentiometers. The stereo
signal is then sent to a X10 gain stage (U1 etc.) and on to the dry side of the mix potentiometer, as
well as summed to mono (Via R21, R22).
The summed stereo signal is sent to the anti-aliasing filter consisting of most of U4, and
associated resistors and capacitors. There are several important features in the filter to be aware of.
The first is the use of the LSTMSB (See section 4.5 for a description) signal from the ASIC. This
signal is injected into the signal path at U4 pin 12. A signal diode at U4 pin 10 limits the incoming
signal to 5V, preventing damage to the analog switch (U6). The output of U4 pin 8 has a tap running
to R46, a 2N4401 transistor, etc., and eventually on to an 8031 input port (U27 pin 13) where it is
used to detect the audio threshold level necessary for triggered flange and gated reverb.
The input sample and hold circuit consists of 1/3 of the 4053 analog switch (U6B), the input
sample cap (C29), a buffer amplifier (U4), and a comparator (U5). Also note the differential amplifier
(R44, R52, R53, 2 signal diodes, 2 NPN transistors) just prior to the comparator. This diff-amp
speeds up the response time of the comparator.
The signal beyond this point is purely digital, until the DAC output cycle of the DASP 8. At the
appropriate time, the DAC will output the processed left, and right signals. This action is coordinated
with the two output sample and hold circuits (U6A&C, 2 op amps of U3, C22, C23), so that each
receives the correct, separate signal for stereo output. After passing through low pass (anti aliasing)
filters (2 op amps of U3, Misc. Resistors & Capacitors), the signals are buffered (2 op amps of U2),
and sent through the output potentiometers. From here, they pass through unity gain amps (2 op
amps of U2), through impedance fixing resistors (R5, R10) and R.F. suppression toroids, to the
output jacks (J3, J4).
Diagram 2
When the switch is turned off, the capacitor will hold that level
indefinitely [barring internal leakage ]. At this point, the SAR
(Successive Approximation Register-part of the DASP 8 ASIC)
will take over. Starting with the MSB, the SAR will set the bit,
and compare the output of the DAC, to the level of the input sample capacitor (via comparator U5).
The results of the comparison are stored in the register, and the next most significant bit is

3.1 SUCCESSIVE APPROXIMATION

Successive approximation is an empirical approach to the
process of analog to digital conversion. The idea is to divide the
process into short,
manageable sections.
Each significant binary
weight (starting with the
Most Significant Bit) is
taken in turn, thus requiring
only 16 comparisons to
achieve a final value.
The process begins
with the input "sample and
hold" circuit. 1/3 of the
4053 (U6B) is turned on,
allowing the input sample
capacitor (C44) to charge
[or discharge] to the level
of the current input signal.
Diagram 3