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10 STOPWaTCh TiMeR
10.3
Counter and Prescaler
The stopwatch timer is configured of four-bit BCD counters SWD[3:0], SWD[7:4] and SWD[11:8].
The counter SWD[3:0], at the stage preceding the stopwatch timer, has a 1,000 Hz signal generated by
the prescaler for the input clock. It counts up every 1/1,000 sec, and generates 100 Hz signal. The coun-
ter SWD[7:4] has a 100 Hz signal generated by the counter SWD[3:0] for the input clock. It count-up every
1/100 sec, and generated 10 Hz signal. The counter SWD[11:8] has an approximated 10 Hz signal generated by the
counter SWD[7:4] for the input clock. It count-up every 1/10 sec, and generated 1 Hz signal.
The prescaler inputs a 1,024 Hz clock dividing f
Hz counting clock for SWD[3:0]. To generate a 1,000 Hz clock from 1,024 Hz, 24 pulses from 1,024 pulses that are
input to the prescaler every second are taken out.
When the counter becomes the value indicated below, one pulse (1,024 Hz) that is input immediately after to the
prescaler will be pulled out.
<Counter value (msec) in which the pulse correction is performed>
39, 79, 139, 179, 219, 259, 299, 319, 359, 399, 439, 479, 539, 579, 619, 659, 699, 719, 759, 799, 839, 879, 939,
979
Figure 10.3.1 shows the operation of the prescaler.
Prescaler input clock (1,024 Hz)
Prescaler output clock
Counter data
For the above reason, the counting clock is 1,024 Hz (0.9765625 msec) except during pulse correction. Conse-
quently, frequency of the prescaler output clock (1,000 Hz), 100 Hz generated by SWD[3:0] and 10 Hz generated by
SWD[7:4] are approximate values.
10.4
Capture Buffer and hold Function
The stopwatch timer data, 1/1,000 sec, 1/100 sec and 1/10 sec, can be read from SWD[3:0] (FF4BH), SWD[7:4]
(FF4CH) and SWD[11:8] (FF4DH), respectively. The counter data are latched in the capture buffer when reading,
and are held until reading of three words is completed. For this reason, correct data can be read even when a carry
from lower digits occurs during reading the three words. Further, three counter data are latched in the capture buffer
at the same time when SWD[3:0] (1/1,000 sec) is read. The data hold is released when SWD[11:8] (1/10 sec) read-
ing is completed. Therefore, data should be read in order of SWD[3:0] → SWD[7:4] → SWD[11:8]. If SWD[7:4]
or SWD[11:8] is first read when data have not been held, the hold function does not work and data in the counter
is directly read out. When data that has not been held is read in the stopwatch timer RUN status, you cannot judge
whether it is correct or not.
The S1C63004/008/016 stopwatch timer has a LAP function using an external key input (explained later). The cap-
ture buffer is also used to hold LAP data. In this case, data is held until SWD[11:8] is read. However, when a LAP
input is performed before completing the reading, the content of the capture buffer is renewed at that point. Remain-
ing data that have not been read become invalid by the renewal, and the hold status is not released if SWD[11:8] is
read. When SWD[11:8] is read after the capture buffer is updated, the capture renewal flag CRNWF is set to "1" at
that point. In this case, it is necessary to read from SWD[3:0] again. The capture renewal flag is renewed by reading
SWD[11:8].
Figure 10.4.1 shows the timing for data holding and reading.
10-2
(output from the OSC1 oscillation circuit), and outputs 1,000
OSC1
START
000 001 002
Figure 10.
3.1 Timing of the prescaler operation
Seiko epson Corporation
037 038
039
040 041
S1C63003/004/008/016 TeChniCal Manual
(Rev. 1.1)
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