Stopwatch Counter; Configuration Of Stopwatch Counter - Epson S1C6S3N2 Technical Manual

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Counter)
Configuration of

stopwatch counter

Fig. 4.9.1
Block diagram of
stopwatch counter
I-66
4.9 Stopwatch Counter
The S1C6S3N2 Series incorporates a 1/100 sec and 1/10
sec stopwatch counter. The stopwatch counter is configured
of a two-stage, four-bit BCD counter serving as the input
clock of an approximately 100 Hz signal (signal obtained by
approximately demultiplying the 256 Hz signal output by
the prescaler). Data can be read out four bits at a time by
the software.
Figure 4.9.1 is the block diagram of the stopwatch counter.
OSC1
oscillation
circuit
Stopwatch counter reset signal
Stopwatch counter RUN/STOP signal
The stopwatch counter can be used as a separate timer from
the clock timer. In particular, digital watch stopwatch
functions can be realized easily with software.
Data bus
256 Hz
10 Hz
SWL counter
EPSON
SWH counter
10 Hz,1 Hz
Interrupt
Interrupt request
control
S1C6S3N2 TECHNICAL HARDWARE