LG CU920 Manual page 69

The MEGA Camera module is
connected to 34pin connector
(AXK7L34227G). Its interface is
dedicated camera interface port in
MSM6281. The camera port supply
24.576MHz master clock to camera
module and receive 40.2MHz pixel
clock (15fps), vertical sync signal,
horizontal sync signal, reset signal
and 8bits data from camera module.
The camera module is controlled by
I2C port from MSM6281.
Table. Interface between MEGA
Camera Module and MAIN PCB
(in camera module)
Copyright © 2008 LG Electronics. Inc. All right reserved.
Only for training and service purposes
No Name
1 GND
2 CAM_PCLK
3 GND
4 GND
5 CAM_RESET_N
6 GND
7 N/A
8 I2C_SDA
9 I2C_SCL
10 N/A
11 N/A
12 GND
13 CAM_PWDN
14 VREG_CAM_ACT
15 VREG_CAM_ACT
16 VREG_CAM_2.8V
17 VREG_CAM_2.8V
18 CAM_HSYNC
19 CAM_VSYNC
20 GND
21 CAM_MCLK
22 GND
23 CAM_DATA(0)
24 CAM_DATA(1)
25 CAM_DATA(2)
26 CAM_DATA(3)
27 CAM_DATA(4)
28 CAM_DATA(5)
29 CAM_DATA(6)
30 CAM_DATA(7)
31 VREG_CAM_IO_2.8V
32 VREG_CAM_IO_2.8V
33 VREG_CAM_1.8V
34 VREG_CAM_1.8V
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3. TECHNICAL BRIEF
Port Note
GND GND
O Pixel Clock
GND GND
GND GND
I Camera reset signal
GND GND
N/A N/A
I/O I2C Data
I/O I2C Clock
N/A N/A
N/A N/A
GND GND
I Camera power down
I VDDIO 2.8v
I VDDIO 2.8v
I VDDA 2.8v
I VDDA 2.8v
O Horizonal Sync
O Vertical Sync
GND GND
I Master Clock(24.576M)
GND GND
O DATA
O DATA
O DATA
O DATA
O DATA
O DATA
O DATA
O DATA
I VDDCAM 2.8v
I VDDCAM 2.8v
I VDDD 1.5v
I VDDD 1.5v
LGE Internal Use Only