Minimizing The Deadtimes; Processing Sequence Within A Basic Cpu Clock Cycle; Interconnection Changes And Limited Number Of Interconnections - Siemens SIMADYN D Manual

2.1.6.6 Minimizing the deadtimes

2.1.6.7 Processing sequence within a basic CPU clock cycle

2.1.6.8 Interconnection changes and limited number of interconnections

Interconnection
changes during the
configuring test
phase
System- and communication configuring D7-SYS - SIMADYN D
Edition 03.2001
To minimize the deadtimes, a signal can be directly transferred,
bypassing the data consistency mechanism. It can be directly
"connected" to the output of the generating block. They are two ways to
configure this:
• Pseudo comment @DATX for interconnecting tasks of a CPU
• Fast $ signals for interconnecting several CPUs
The task administrator (refer to the Chapter "Mode of operation of the
task administrator") of the operating system is started with the basic CPU
clock cycle T0. This then decides which tasks are to be started (T1 and
maximum of one other Tn,
with Tn from {T2...T5}.
Essentially, the following components are to be executed within the task
processing:
• Buffer changeover for the tasks to be started (T1 and, if required an
additional task Tn)
• System mode of the blocks in T1 corresponding to the module
sequence (refer to the Chapter "Significance and uses of the process
image")
• System mode of blocks in Tn corresponding to the block sequence
(refer to the Chapter "Significance and uses of the process image");
• Importing signal interconnections in the T1 and standard mode
T1
• Exporting signal interconnections from T1
• Importing signal interconnections in Tn and standard mode Tn
• Exporting signal interconnections from Tn
The components relevant for signal transfer are highlighted.
Interconnections extending beyond the task limits can only be changed
with some restrictions using the test mode of the CFC editor. The CFC
editor test mode is used to test and optimize the user program, which is
already running online on the CPU.
Systemsoftware
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