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Siemens C16 Series Instruction Set Manual page 31

16-bit cmos single-chip microcontrollers

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Representation in the
Assembler Listing:
Internal Organization:
Figure 5-1: Instruction Format Representation
Notes on the ATOMIC and EXTended Instructions
These instructions (ATOMIC, EXTR, EXTP, EXTS, EXTPR, EXTSR) disable standard and PEC
interrupts and class A traps during a sequence of the following 1...4 instructions. The length of the
sequence is determined by an operand (op1 or op2, depending on the instruction). The EXTended
instruction additionally change the addressing mechanism during this sequence (see detailled
instruction description).
The ATOMIC and EXTended instructions become active immediately, so no additional NOPs are
required. All instructions requiring multiple cycles or hold states to be executed are regarded as one
instruction in this sense. Any instruction type can be used with the ATOMIC and EXTended
instructions.
CAUTION: When a Class B trap interupts an ATOMIC or EXTended sequence, this sequence is
terminated, the interrupt lock is removed and the standard condition is restored, before the trap
routine is executed! The remaining instructions of the terminated sequence that are executed after
returning from the trap routine will run under standard conditions!
CAUTION: Be careful, when using the ATOMIC and EXTended instructions with other system
control or branch instructions.
CAUTION: Be careful, when using nested ATOMIC and EXTended instructions. There is ONE
counter to control the length of such a sequence, ie. issuing an ATOMIC or EXTended instruction
within a sequence will reload the counter with value of the new instruction.
Note: The ATOMIC and EXTended instructions are not available in the SAB 8XC166(W) devices.
The following pages of this section contain a detailled description of each instruction of the C166
Family in alphabetical order.
Semiconductor Group
30Mar98@15:00h
N2N1
N4N3
High Byte 1st word
Low Byte 1st word
MSB
N8
N7
31
C166 Family Instruction Set
Instruction Description
N6N5
Low Byte 2nd word
Bits in ascending order LSB
N6
N5
N4
N8N7
High Byte 2nd word
N3
N2
N1
Version 1.2, 12.97

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