Siemens C16 Series Instruction Set Manual page 124

The total time ( T tot ), which a particular part of a program takes to be processed, can be calculated
by the sum of the single instruction processing times ( T In ) of the considered instructions plus an
offset value of 6 state times which considers the solitary filling of the pipeline, as follows:
T tot =
The time T In , which a single instruction takes to be processed, consists of a minimum number
( T Imin ) plus an additional number ( T Iadd ) of instruction state times and/or ALE Cycle Times, as
follows:
T In =
Minimum State Times
The table below shows the minimum number of state times required to process an instruction
fetched from the internal ROM ( T Imin (ROM)). The minimum number of state times for instructions
fetched from the internal RAM ( T Imin (RAM)), or of ALE Cycle Times for instructions fetched from
the external memory ( T Imin (ext)), can also be easily calculated by means of this table.
Most of the 16-bit microcontroller instructions - except some of the branches, the multiplication, the
division and a special move instruction - require a minimum of two state times. In case of internal
ROM program execution there is no execution time dependency on the instruction length except for
some special branch situations. The injected target instruction of a cache jump instruction can be
considered for timing evaluations as if being executed from the internal ROM, regardless of which
memory area the rest of the current program is really fetched from.
For some of the branch instructions the table below represents both the standard number of state
times (ie. the corresponding branch is taken) and an additional T Imin value in parentheses, which
refers to the case that either the branch condition is not met or a cache jump is taken.
Minimum Instruction State Times [Unit = ns]
Instruction
CALLI, CALLA
CALLS, CALLR, PCALL
JB, JBC, JNB, JNBS
JMPS
JMPA, JMPI, JMPR
MUL, MULU
DIV, DIVL, DIVU, DIVLU
MOV[B] Rn, [Rm+#data16]
RET, RETI, RETP, RETS
TRAP
All other instructions
Semiconductor Group
30Mar98@15:00h
T I1 + T I2 + ... + T In + 6
T Imin + T Iadd
C166 Family Instruction Set
States
*
T Imin (ROM)
[States]
4 (+2)
4
4 (+2)
4
4 (+2)
10
20
4
4
4
2
124
Instruction State Times
T Imin (ROM)
(@ 20 MHz CPU clock)
200
200
200
200
200
500
1000
200
200
200
100
Version 1.2, 12.97
(+100)
(+100)
(+100)