External Interfaces; Clock Generation; Liquid Crystal Display (Lcd); Configuration Init And Done Leds - Xilinx Virtex-4 ML461 User Manual

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External Interfaces

The external interfaces of the Virtex-4 ML461 Development Board are described in this
section.

Clock Generation

The clock generation section of the ML461 Development Board provides all necessary
clocks for the four Virtex-4 FPGAs. Three clock sources are provided to each FPGA as
follows:
•
•
•

Liquid Crystal Display (LCD)

The Virtex-4 ML461 Development Board provides an 8-bit interface to a 64 x 128 LCD
panel (DisplayTechQ 64128E-FC-BC-3LP, 64 x 128). The LCD is attached to the board via
the receptacle connector P55 and four stand-offs. This display was chosen because of its
possible use in embedded systems. Refer to the product specification at
http://www.displaytech.com.hk/pdf/graphic/64128e%20series-v10.PDF
information.

Configuration INIT and DONE LEDs

The Virtex-4 ML461 Development Board provides an INIT LED and a DONE LED, which
can be turned ON by driving the LEDs signal Low.
their associated pin assignments for the FF668 FPGA used on the Virtex-4 ML461
Development Board.
Table 3-9: Configuration INIT and DONE LED Pin Assignments
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
A 200 MHz differential LVPECL oscillator (Epson EG2121CA 2.5V at Y3)
This oscillator is required for the IDELAY tap controller for Virtex-4 devices. A
differential clock buffer (ICS853006 from
generate four LVPECL copies of the differential clock signal, one for each FPGA.
(DIRECT_CLK_TO_FPGAx_[P,N])
An external signal generator SMA connector (J2, J3) interface
An LVDS differential clock can be provided to the board via a pair of SMA connectors.
Another differential clock buffer (ICS853006) is used on the board (U12) to generate
four LVPECL copies of the differential clock signal, one for each FPGA
(EXT_CLK_TO_FPGAx_[P,N]).
A high-frequency synthesized clock interface
A 33 MHz oscillator (EPSON SG-8002CA) on the board (Y1) provides a single-ended,
low-frequency clock. Four copies of this clock are generated using a clock buffer
(ICS8304) on the board (U8). Each of these copies is an input to a dedicated clock
synthesizer (ICS8430), one per FPGA (SYNTH_CLK_TO_FPGAx_[P,N]).
Appendix B, "LCD Interface,"
LED
FPGA_INIT
FPGA_DONE
www.xilinx.com
ICS Technology) is used on the board (U13) to
describes the LCD operation in detail.
Table 3-9 describes these LEDs and
Designation
INIT (D19)
DONE (D20)
External Interfaces
for more
FPGA Pin Number
(FF668 Package)
G15
H14
27