Sony Aiwa CX-JD5 Service Manual page 84

CX-JD5
Pin No. Pin Name
117 RFIN
118, 119
VCCA5, VCCA4
120 VCOR1
121 VCOIN
122, 123
GNDA4, GNDA3
124 LPF5
125 VC1
126, 127 LPF2, LPF1
128, 129
VCCA3, VCCA2
130 PDO
131 PDHVCC
132 FDO
133, 134
GNDA2, GNDA1
135 SPO
136 VC2
137 MDIN2
138 MDIN1
139 VCCA1
140 CLVS
141 VSS
142 MDSOUT
143 VDD
144 MDPOUT
145 DEFECT
146 GSCOR
147 EXCK
148 SBIN
149 VSS
150 SCOR
151 WFCK
152 VDD5V
153 XRCI
154 VDDS
155 C2PO
156 VDD
157 DBCK
158 BCLK
159 DDAT
160 MDAT
161 VSS
162 DLRC
163 LRCK
164 XRST
165 IFS0
166 IFS1
167 XTAL
84
I/O
I RF signal input from the CD/DVD RF amplifier
— Power supply (+3.3V)
— VCO oscillating range setting resistor connected
I VCO input
— Ground
O Signal output from the operation amplifier from PLL loop filter
I Middle point voltage (+1.65V) input
I Inverted signal input to the operation amplifier from PLL loop filter
— Power supply (+3.3V)
O Signal output from the charge pump for phase comparator
I Middle point voltage input terminal for RF PLL
O Signal output from the charge pump for frequency comparator
— Ground
O Spindle motor control signal output to FAN8035L
I Middle point voltage (+1.65V) input
I Spindle motor servo drive signal input
I MDP input
— Power supply (+3.3V)
O Control signal output for selection the spindle control filter constant at CLVS
— Ground
O Frequency error output terminal of internal CLV circuit
— Power supply (+3.3V)
O Phase error output of internal CLV circuit
I Defect signal input (Not used)
I Guard subcode sync (S0+S1) detection signal input from CXD3068Q
O Subcode serial data reading clock signal output to CXD3068Q
I Subcode serial data input from CXD3068Q
— Ground
I Subcode sync (S0+S1) detection signal input from CXD3068Q
I Write frame clock signal input from CXD3068Q
— Power supply (+5V)
I Not used (Pull down)
— Power supply (+5V)
I C2 pointer signal input from CXD3068Q
— Power supply (+3.3V)
O Bit clock signal (2.8224 MHz) output (Not used)
I Bit clock signal (2.8224 MHz) input from CXD3068Q
O PCM data (Not used)
I Serial data input from CXD3068Q
— Ground
O L/R sampling clock signal (Not used)
I L/R sampling clock signal (44.1 kHz) input from CXD3068Q
I Reset signal input from CXP973064-226R "L": reset
I Not used (connected to ground)
I Not used (connected to VDD)
I 33.8688 MHz clock signal input from SM8707GV
Description