Vizio P42HDTV10A Service Manual page 76

Write
The Write command is used to initiate a burst write access to an active (open) row. The value on
the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9,
j = don't care] for x8; where [i = 9, j = 11] for x4) selects the starting column location. The value
on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected,
the row being accessed is precharged at the end of the Write burst; if Auto Precharge is not
selected, the row remains open for subsequent accesses. Input data appearing on the DQs is
written to the memory array subject to the DM input logic level appearing coincident with the data.
If a given DM signal is registered low, the corresponding data is written to memory; if the DM
signal is registered high, the corresponding data inputs are ignored, and a Write is not executed
to that byte/column location.
Auto Refresh
Auto Refresh is used during normal operation of the DDR SDRAM and is analogous to CAS
Before RAS (CBR) Refresh in previous DRAM types. This command is nonpersistent, so it must
be issued each time a refresh is required.
The refresh addressing is generated by the internal refresh controller. This makes the address
bits "Don't Care" during an Auto Refresh command. The 256Mb DDR SDRAM requires Auto
Refresh cycles at an average periodic interval of 7.8μs (maximum).
Self Refresh
The Self Refresh command can be used to retain data in the DDR SDRAM, even if the rest of the
system is powered down.When in the self refresh mode, the DDR SDRAM retains data without
external clocking. The Self Refresh command is initiated as an Auto Refresh command
coincident with CKE transitioning low. The DLL is automatically disabled upon entering Self
Refresh, and is automatically enabled upon exiting Self Refresh (200 clock cycles must then
occur before a Read command can be issued). Input signals except CKE (low) are "Don't Care"
during Self Refresh operation.
The procedure for exiting self refresh requires a sequence of commands. CK (and CK) must be
stable prior to CKE returning high. Once CKE is high, the SDRAM must have NOP commands
issued for tXSNR because time is required for the completion of any internal refresh in progress.
A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200 clock
cycles before applying any other command.
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