Vizio P42HDTV10A Service Manual page 47

7. Burst Read Operation
Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that
the Burst read command is issued by asserting CS and CAS low while holding RAS and WE
high at the rising edge of the clock (CLK) after tRCD from the bank activation. The address
inputs determine the starting address for the Burst, The Mode Register sets type of burst.
(Sequential or interleave) and burst length (2, 4, 8). The first output data is available after the
CAS Latency from the READ command, and the consecutive data are presented on the falling
and rising edge of Data Strobe (DQS) adopted by DDR SDRAM until the burst length is
completed.
8. Burst Write Operation
The Burst Write command is issued by having CS , CAS and WE low while holding RAS high
at the rising edge of the clock (CLK). The address inputs determine the starting column
address. There is no write latency relative to DQS required for burst write cycle. The first data
of a burst write cycle must be applied on the DQ pins tDS (Data-in setup time) prior to data
strobe edge enabled after tDQSS from the rising edge of the clock (CLK) that the write
command is issued. The remaining data inputs must be supplied on each subsequent falling
and rising edge of Data Strobe until the burst length is completed. When the burst has been
finished, any additional data supplied to the DQ pins will be ignored.
CONFIDENTIAL – DO NOT COPY Page 8-15
File No. SG-0184