Vizio P42HDTV10A Service Manual
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Vizio P42HDTV10A Service Manual

V, inc. portable tv service manual
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Summary of Contents for Vizio P42HDTV10A

  • Page 2: Table Of Contents

    9. Waveforms 10. Trouble Shooting 11.Spare Parts List 12. Complete Parts List Appendix 1. Main Board Circuit Diagram 2. Main Board PCB Layout 3. Assembly Explosion Drawing Block Diagram Table of Contents VIZIO P42HDTV10A Service Manual PAGE 10-1 11-1 12-1...
  • Page 3 Use a power cable that is properly grounded. Always use the AC cords as follows – USA (UL); Canada (CSA); Germany (VDE); Switzerland (SEV); Britain (BASEC/BS); Japan (Electric Appliance Control Act); or an AC cord that meets the local safety standards. VIZIO P42HDTV10A Service Manual...

  • Page 4: Features

    Chapter 1 Features 1024 x 768 pixel resolution with 16:9 wide screen ATSC (Off-air)/QAM (Cable)/NTSC (Antenna/Cable) All TV formats supported (480i, 480p, 720p & 1080i) PC compatible (RGB) up to 1280 x 1024 WXGA High definition digital interface - HDMI Multiple-screen display (picture-on-picture/picture-in-picture) Selectable picture mode Supporting DVI converted to HDMI...

  • Page 5: Specifications

    Chapter 2 Specification 1. General specification Native Resolution Effective Display Size Aspect Ratio Color Brightness (w/glass filter) Contrast Ratio TV system PC Inputs Video Inputs Audio Inputs Audio Outputs Audio Power Input Power Consumption Preset Modes CONFIDENTIAL – DO NOT COPY 1024 (H)X768 (V) pixels, 921.6 (H) x 519.2 (V) mm 16:9...

  • Page 6: Optical Characteristics

    2. Optical characteristics Item Display Pixels Display Cells Pixel Pitch Pixel Type Color Depth Active Display Area Brightness Color coordinates 3. Power Supply a. Input voltage b. Input current c. Inrush current d. Power consumption 380 W Max e. Standby/DPMS 4.
  • Page 7 5. Dimensions Item a. Height b. Width c. Depth 6. Weight a. Net: 38.8 +/- 0.5 b. Gross: 47.5 +1.5 CONFIDENTIAL – DO NOT COPY W/Stand 780 mm 1072mm 290 mm /- 0.5 W/O stand 755 mm 1072mm 109 mm Page 2-3 File No.

  • Page 8: On Screen Display

    Chapter 3 On Screen Display Input Menu Operation Menu TV Mode CONFIDENTIAL – DO NOT COPY A. PICTURE ADJUST： a. PICTURE MODE (USER/ VIVID1 / VIVID2 / VIVID3) b. Adjust the BRIGHTNESS (0~100) c. Adjust the CONTRAST (0~100) d. Adjust the COLOR (saturation) (0~100) e.
  • Page 9 CONFIDENTIAL – DO NOT COPY C. TV TUNER SETUP： a. SOUND (SAP/MONO/STEREO) b. TV/CABLE (TV/CABLE) c. CHANNEL SEARCH (RUN) d. SET CHANNEL e. SKIP CHANNEL (YES/NO) D. PARENTAL CONTROL： a. PARENT LOCK ENABLE (ON/OFF) b. TV RATING MOVIE RATING d. ACCESS CODE EDIT E.
  • Page 10 RGB Mode CONFIDENTIAL – DO NOT COPY A. PICTURE ADJUST： a. AUTO ADJUST b. Adjust the BRIGHTNESS (0~100) Adjust the CONTRAST (0~100 d. Adjust the H-SIZE (0~100) e. Adjust the H-POSITION (0~100) Adjust the V-POSITION (0~100) g. Adjust the FINETUNE (0~100) B.
  • Page 11 HDMI Mode CONFIDENTIAL – DO NOT COPY E. SPECIAL FEATURES： a. LANGUAGE (ENGLISH/FRANÇAIS/ ESPAÑOL) b. SLEEP TIMER (OFF/30/60/90/120) WIDE FORMAT (WIDE/NORMAL) d. RESET ALL SETTING e. IMAGE CLEANER A. PICTURE ADJUST： PICTURE MODE (USER/ VIVID1 / VIVID2 / VIVID3) Adjust the BRIGHTNESS (0~100) Adjust the CONTRAST (0~100) Adjust the COLOR (saturation) (0~100) Adjust the TINT (hue) (0~100)
  • Page 12 CONFIDENTIAL – DO NOT COPY D. PIP SETUP： a. STYLE (OFF/PIP/POP) b. SOURCE (AV1、AV2、AV3、TV) c. SIZE (SMALL /MEDIUM/LARGE) d. POSITION (TOP LEFT/TOP CENTER/TOP RIGHT/MIDDLE LEFT/MIDDLE RIGHT/BOTTOM LEFT/BOTTOM CENTER/BOTTOM RIGHT) E. SPECIAL FEATURES： a. LANGUAGE (ENGLISH/FRANÇAIS/ ESPAÑOL) b. SLEEP TIMER (OFF/30/60/90/120) c.
  • Page 13 Video Mode - AV1、AV2、AV3、COMPONENT 1、COMPONENT 2 CONFIDENTIAL – DO NOT COPY A. PICTURE ADJUST： a. PICTURE MODE (USER/ VIVID1 / VIVID2 / VIVID3) b. Adjust the BRIGHTNESS (0~100) c. Adjust the CONTRAST (0~100) d. Adjust the COLOR (saturation) (0~100) e. Adjust the TINT (hue) (0~100) Adjust the SHARPNESS (0~100) g.
  • Page 14 DTV Mode CONFIDENTIAL – DO NOT COPY E. SPECIAL FEATURES： a. LANGUAGE (ENGLISH/FRANÇAIS/ ESPAÑOL) b. SLEEP TIMER (OFF/30 MIN/60 MIN /90 MIN/120 MIN) c. WIDE FORMAT (NORMAL/WIDE/ZOOM) d. RESET ALL SETTING e. IMAGE CLEANER A. DTV TUNER SETUP a. TIME ZONE: 1.HAWALL 2.EASTTERN TIME 3.INDIANA...
  • Page 15 CONFIDENTIAL – DO NOT COPY e. CHANNEL SKIP f. DIGITAL AUDIO OUT 1. PCM 2. DOLBY DIGITAL 3. OFF B.CLOSED CAPTION: a. ANALOG CLOSED CAPTION (OFF/YES) b. DIGITAL CLOSED CAPTION (OFF/YES) c. DIGITAL CAPTION STYLE 1.AS BROADCASTER 2.CUSTOM (1) FONT SIZE α.LARGE β.SMALL γ.MEDIUM...
  • Page 16 CONFIDENTIAL – DO NOT COPY β.WHITE γ.GREEN δ.BLUE ε.RED ζ.CYAN η.YELLOW θ.MAGENTA (3) FONT OPACITY α.SOLID β.TRANSLUCENT γ.TRANSPARENT (4)BLACKGROUND COLOR α.BLACK β.WHITE γ.GREEN δ.BLUE ε.RED ζ.CYAN η.YELLOW θ.MAGENTA (5) BLACKGROUND OPACITY α.SOLID β.TRANSLUCENT γ.TRANSPARENT (6) WINDOW COLOR α.BLACK β.WHITE γ.GREEN δ.BLUE ε.RED ζ.CYAN...
  • Page 17 PIP table MAIN COMPONENT 1 COMPONENT 2 HDMI * Sub/HDMI doesn’t support 1080i. CONFIDENTIAL – DO NOT COPY C. PASSWORD - PRESS<OK> , enter 0000 - get to “CHANNEL BLOCK”, then press <OK> COMPONENT 1 COMPONENT 2 HDMI* RGB File No. SG-0184 Page 3-10...

  • Page 18: Factory Preset Timings

    Chapter4 Factory preset timings This timing chart is already preset for the analog & digital displays.. 1. RGB PC preset modes Refresh Mode Resolution Rate (Hz) 640x480 640x480 720 x 400 800x600 800x600 800x600 1024x768 1024x768 1024x768 1280X1024 Remark: P: positive, N: negative 2.
  • Page 19 3. HDMI-DVI video preset modes 4. HDMI-DVI PC preset modes Refresh Mode Resolution Rate (Hz) 640x480 CONFIDENTIAL – DO NOT COPY Mode No. Resolution 480i 480p 720p 1080i Horizontal Horizontal Vertical Frequency Frequency (KHz) (Hz) 31.5 59.94 Vertical Pixel Sync Sync Rate Polarity...

  • Page 20: Pin Assignment

    Chapter 5 Pin Assignment There are analog and digital connectors as video input source in this model. A. Input signal 1. RGB PC Connector a. Type: b. Frequency: c. Signal level: d. Impedance: e. Synchronization f. Video bandwidth: g. Connector type: Pin Number Pin Assignment Red video input...
  • Page 21 2. HDMI Connector a. Frequency: b. Polarity: c. Type: d. Pin Assignment: Pin 19 Signal Assignment TMDS Data2+ TMDS Data2- TMDS Data1 Shield TMDS Data0+ TMDS Data0- TMDS Clock Shield DDC/CEC Ground Hot Plug Detect CONFIDENTIAL – DO NOT COPY H: 15.734KHz H: 31KHz H: 45KHz...
  • Page 22 3. AV/Composite Video (CVBS) Connector a. Frequency: H: 15.734KHz b. Signal level: 1Vp-p Sync (H+V):0.3V below Video (Y+C) c. Impedance: 75Ω d. Connector type: RCA jack 4. AV/S-Video Connector a. Frequency: b. Signal level: c. Impedance: d. Connector type: 5. Component video Connector a.
  • Page 23 6. F-type TV RF connector NTSC system a. Signal level b. Frequency ATSC system a. IF-output level b. Frequency QAM system (supporting clear QAM) a. IF-output level b. Frequency 7. PC Stereo audio a. Signal level: b. Impedance: c. Connector type: 8.
  • Page 24 1. Analog Audio out a. Signal level: 0.7Vrms b. Impedance: 47KΩ c. Frequency Response: 250Hz-20KHz d. Connector type: RCA L/R 2. Digital audio out a. Peak emission wave length: 630 – 690 µm b. Transmission Speed: c. Connector type: 3. Headphone a.

  • Page 25: Block Diagram

    Chapter 6 Block Diagram 42’’ PDP XGA panel The TV system block diagram is powered by power board that transforms AC source of 100V~240V AC +/- 10% @ 50/60 HZ into system request power source. The main board receives different types of video signal into the MTK8205 Ic. Afterward, the MTK8205 Ic process the signals control the various functions of the monitor and outputs control signal, video signal and power to the 42’’PDP XGA panel to be displayed.
  • Page 26 The analog video signals of S-video, YPbPr, TV, PC and A/V all video signals are translated from analog signals into MTK8205 generates the vertical and horizontal timing signals for display device. The analog audio of s-video, YPbPr, TV, PC and A/V is transmitting to the WM8776 processed.
  • Page 27 Main Board Block Diagram CONFIDENTIAL – DO NOT COPY Page 6-3 File No. SG-0184...
  • Page 28 Video Board Block Diagram Narrow_IF_OP1&OP2 IF AGC PHILIPS TD1336 CONFIDENTIAL – DO NOT COPY PORT SAW FILTER Amplifiers DDR SDRAM U12,U13 DV33 VOLTAGE CONTROL CRYSTAL OSCILLATOR Demodulator MT5111 DTV Backend Decoder MT5351 IDTQS3VH257 AUD_CTRL Flash Memory Title <Title> Size Document Number <Doc>...

  • Page 29: Main Board I/O Connections

    Chapter7 Main Board I/o Connections J7 C → ONNECTION BOTTOM J1 C ONNECTION CONFIDENTIAL – DO NOT COPY Description “Auto” “Left” “Right” “Down” “Gnd” “Up” “Menu” “Source” “Power” “LED” “IR” “+5V” →B OTTOM Description “POWRSW” “+12V” “+12V” “+12V” “GND” “GND” “GND”...
  • Page 30 J3 C →B ONNECTION CONFIDENTIAL – DO NOT COPY OTTOM Description “SVDET2#” “S1C_GND” “S1C_IN” “S1Y_GND” “S1Y_IN” “AGND” “AV3R” “AV3R GND” “AV3L” “AV3_GND” “AV3_IN” “AV3L GND” “HPL” “HPDET#” “HPR” “GNDV” Page 7-2 File No. SG-0184...
  • Page 31 J2 C →B ONNECTION Description “GND” “I2C_SW” “OREQUEST#” “OREADY#” “ORESET#” “GND” “VOPCLK” “VODE” “VOVSYNC” “VOHSYNC” “GND” “VOR7” “VOR6” “VOR5” “VOR4” “GND” “VOR3” “VOR2” “VOR1” “VOR0” “GND” “VOG7” “VOG6” “VOG5” “VOG4” CONFIDENTIAL – DO NOT COPY OTTOM Description “GND” “VOG3” “VOG2” “VOG1”...
  • Page 32 J8 C →B ONNECTION CONFIDENTIAL – DO NOT COPY OTTOM Description “+5V” “GND” “GND” “+12V” “+12V” Page 7-4 File No. SG-0184...

  • Page 33: Theory Of Circuit Operation

    Chapter 8 Theory of Circuit Operation The operation of D-SUB 15pin route The D-SUB 15pin is input analog signal to the MTK8205 transfer A/D converter then generates the vertical and horizontal timing signals for display device. The operation of HDMII CON route The HDMI CON is input digital signal the signal is process to the sil9011.
  • Page 34 1. The power key through POW and GND to control MTK8205, MTK8205 will receive a low signal to turn on or off system while press the power key. 2. The other key the same as power key . 3. The LED is constructed with two separate LED which color is MTK8205 direct control the LED’s when MTK8205 (OGO5) is low the LED is orange (Close power) when MTK8205 (OGO5) is high the LED is MT8205 Application...
  • Page 35 BOLOCK DIAGRAM 1. Video input a. Input Multiplexing 1.component X2 2.composite X3 3.s-videoX1 4.HDMI X1 5.VGA X1 6.RF X2 CONFIDENTIAL – DO NOT COPY Page 8-3 File No. SG-0184...
  • Page 36 b. Input formats: 1.support HDTV 480i/480p/720p/1080i 2.support Y/C signal 1VP-P/75Ω 3.support Y/C signal 1VP-P/75Ω 4.support 480i/408p/720p/1080i 5.support VGA input up to 6.support NTSC system Frequency 55~801MHZ 7. support ATSC system Frequency 57~863MHZ 2. TV Decoder For pip/pop: Dual identical TVD on chip 3D-comb for both path Dual VBI decoders for the application of V-chip 3.
  • Page 37 BOLOCK DIAGRAM 4. 2D-Graphic/OSD processor Two OSD planes. Support alpha blending among these two planes and video Support text/bitmap decoder Support line/rectangle/gradient fill Support bitblt Support color key function Support clip mask 65535/256/16/4/2-color bitmap format OSD Automatic vertical scrolling of OSD image Support OSD mirror and upside down CONFIDENTIAL –...
  • Page 38 5. Microprocessor interface When power is supplied and power key is pressed then the rest circuit lets Reset to low state that will reset the MTK8205 to initial state. After that the Reset will transits to high state and the MTK8205 start to work that microprocessor executes the programs and configures the internal registers.
  • Page 39 b. PIP/POP HARDWARE LIMITION: Primary Window Source ATSC Tuner NTSC Tuner A/V1 A/V2 A/V3 (Side) Analog HD1 (480i~1080i) Analog HD2 (480i~1080i) G Digital HD1 (HDMI) Input Matrix for Windowing Functionality 6. Video processor a. Color management Flesh tone and multiple-color enhancement Gamma/anti-Gamma correction Color Transient Improvement (CTI) Saturation/hue adjustment...
  • Page 40 c. Scaling Arbitrary ratio vertical/horizontal scaling of video, from1/32X to 32X Advanced linear and non-linear Panorama scaling Programmable Zoom viewer Picture in picture (PIP) Picture in picture d. Display 12/10 10/8 8/6 Dithering processing for 10bit gamma correction Support Alpha blending for Video and two OSD panel Frame rate conversion 7.
  • Page 41 8. Flash Usage Flash is used to store FW code, fonts, bitmaps, and big tables for VGA, Video, and Gamma 2Mbyte is recommended to build a general TV model MTK8205 Flash ROM support test report CONFIDENTIAL – DO NOT COPY Page 8-9 File No.
  • Page 42 DDR SDRAM (M13S128168A-6T) Application Pin description CONFIDENTIAL – DO NOT COPY Page 8-10 File No. SG-0184...
  • Page 43 Command Truth Table 1. Power-Up and Initialization Sequence The following sequence is required for POWER UP and Initialization. 1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.) - Apply VDD before or at the same time as VDDQ. - Apply VDDQ before or at the same time as VTT &...
  • Page 44 6. Issue a mode register set command for “DLL reset”. The additional 200 cycles of clock input is required to lock the DLL.(To issue DLL reset command, provide “High” to A8 and “Low” to BA0) 7. Issue precharge commands for all banks of the device. 8.
  • Page 45 3. Precharge The precharge command is used to precharge or close a bank that has activated. The precharge command is issued when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge each bank respectively or all banks simultaneously.
  • Page 46 4. Row Active The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock (CLK). The DDR SDRAM has four independent banks; so two Bank Select addresses (BA0, BA1) are required. The Bank Activation command to the first read or write command must meet or exceed the minimum of RAS to CAS delay time (tRCD min).
  • Page 47 7. Burst Read Operation Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the Burst read command is issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock (CLK) after tRCD from the bank activation. The address inputs determine the starting address for the Burst, The Mode Register sets type of burst.
  • Page 48 MX29LV160BTTC (Flash) Application The MX29LV800T/B & MX29LV800AT/AB is a 8-mega bit Flash memory organized as 1M bytes of 8 bits or 512K words of 16 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. MX29LV800T/B &...
  • Page 49 BLOCK DIAGRAM 1. COMMAND DEFINITIONS Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table 5 defines the valid register command sequences.
  • Page 50 2. WRITE COMMANDS/COMMAND SEQUENCES To program data to the device or erase sectors of memory, the system must drive WE and CE to VIL, and OE to VIH. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a byte, instead of four.
  • Page 51 After the system writes the auto select command sequence, the device enters the auto select mode. The system can then read auto select codes from the internal register (which is separate from the memory array) on Q7-Q0. Standard read cycle timings apply in this mode. Refer to the Auto select Mode and Auto select Command Sequence section for more information.
  • Page 52 4. READING ARRAY DATA The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Automatic Program or Automatic Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode.
  • Page 53 MT5111 Application: MT5111 Functional Block Diagram MT5111 is fully integrated single-chip 8-VSB , designed specifically for the digital terrestrial. HDTV receivers . The chip is fully compliant with the ATSC A/53 digital TV standard. MT5111 includes a 10-bit A/D converter , 8-VSB demodulator , TCM(Trellis-Coded Modulation). Decoder .
  • Page 54 The carrier frequency offset and symbol timing offset are both estimated and compensated by a fully digital synchronizer . The synchronizer also controls the rate conversion in the digital re-sampling device by estimating the sampling frequency offset . All synchronization in MT5111 are integrated in digital circuits , no external VCXO is required.
  • Page 55 8. 25MHZ crystal for clock generation 9. Full-digital timing recovery , no VCXO is required 10. Full-digital frequency offset recovery with wide acquisition range –1MHZ~+1MHZ 11. Dual digital AGC control for IF and RF respectively 12. MPEG-2 transport stream output in parallel or serial format 13.
  • Page 56 General Feature List : A . Host CPU: 1. ARM 926EJ 2.16K I-Cache and 16K D-Cache 3. 8K Data TCM and 8K instruction 4. JTAG ICE interface 5. Watch Dog timers B . Transport Demuxer : 1. Support 3 independent transport stream inputs 2.
  • Page 57 G . Video Processing : 1. Advanced Motion adaptive de-interlace on SDTV resolution. 2. Support clip 3. 3:2/2:2 pull down source detection. 4. Arbitrary ratio vertical/horizontal scaling of video , from 1/15X to 16X. 5. Support Edge preserve. 6. Support horizontal edge enhancement. 7.
  • Page 58 M . Peripheral Bus Interface : 1. Support NOR/NAND flash. 2. Support CableCard host control bus. N . Audio : 1. Support Dolby Digital AC-3 decoding. 2. MPEG-1 layer I/II , MP3 decoding. 3. Dolby prologic II. 4. Main audio output : 5.1ch + 2ch ( down mix ) 5.
  • Page 59 MX29LV320BTTC (Flash) Application : The MX29LV320AT/B is a 32-mega bit Flash memory organized as 4M bytes of 8 bits and 2M words of 16 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29LV320AT/B is packaged in 48-pin TSOP and 48-ball CSP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers.
  • Page 60 CONFIDENTIAL – DO NOT COPY Page 8-28 File No. SG-0184...
  • Page 61 BLOCK DIAGRAM CONFIDENTIAL – DO NOT COPY Page 8-29 File No. SG-0184...
  • Page 62 BUS OPERATION--1 Legend: L=Logic LOW=VIL, H=Logic High=VIH, VID=12.0 0.5V, V AIN=Address IN, DIN=Data IN,DOUT=Data OUT Notes: 1. When the WP/ACC pin is at VHH, the device enters the accelerated program mode. See "Accelerated Program Operations" for more information. 2.The sector group protect and chip unprotect functions may also be implemented via programming equipment.
  • Page 63 BUS OPERATION--2 Notes: 1.Code=00h means unprotected, or code=01h protected. 2.Code=99 means factory locked, or code=19h not factory locked. WRITE COMMANDS/COMMAND SEQUENCES To program data to the device or erase sectors of memory , the system must drive WE and CE to VIL, and OE to VIH.
  • Page 64 TABLE A. MX29LV320AT/B COMMAND DEFINITIONS Legend: X=Don't care RA=Address of the memory location to be read. RD=Data read from location RA during read operation. PA=Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE or CE pulse. PD=Data to be programmed at location PA.
  • Page 65 STANDBY MODE MX29LV320AT/B can be set into Standby mode with two different approaches. One is using both CE and RESET pins and the other one is using RESET pin only. When using both pins of CE and RESET, a CMOS Standby mode is achieved with both pins held at Vcc ±0.3V.
  • Page 66 The system can thus monitor RY/BY to determine whether the reset operation is complete. If RESET is asserted when a program or erase operation is not executing (RY/BY pin is "1"), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET pin returns to VIH.
  • Page 67 Table B. Write Operation Status Notes: 1.Performing successive read operations from the erase-suspended sector will cause Q2 to toggle. 2.Performing successive read operations from any address will cause Q6 to toggle. 3.Reading the byte/word address being programmed while in the erase-suspend program mode will indicate logic "1"...
  • Page 68 Fig D. READ TIMING WAVEFORMS CONFIDENTIAL – DO NOT COPY Page 8-36 File No. SG-0184...
  • Page 69 Fig E. RESET TIMING WAVEFORM CONFIDENTIAL – DO NOT COPY Page 8-37 File No. SG-0184...
  • Page 70 DDR SDRAM (NT5DS16M16CS-5T) Application : Functional Description The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268, 435, 456 bits. The 256Mb DDR SDRAM is internally configured as a quad-bank DRAM. The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins.
  • Page 71 Block Diagram (16Mb x 16) Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals.
  • Page 72 Pin Configuration - 400mil TSOP II (x4 / x8 / x16) CONFIDENTIAL – DO NOT COPY Page 8-40 File No. SG-0184...
  • Page 73 Mode Register Operation Operating Mode The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register Set command with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values.
  • Page 74 Extended Mode Register The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include DLL enable/disable, bit A0; output drive strength selection, bit A1; and QFC output enable/disable, bit A2 (NTC optional). These functions are controlled via the bit settings shown in the Extended Mode Register Definition.
  • Page 75 Truth Table a: Commands 1. CKE is high for all commands shown except Self Refresh. 2. BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects ,Extended Mode Register; other combinations of BA0-BA1 are reserved;...
  • Page 76 Write The Write command is used to initiate a burst write access to an active (open) row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don’t care] for x8; where [i = 9, j = 11] for x4) selects the starting column location. The value on input A10 determines whether or not Auto Precharge is used.
  • Page 77 Operations : Reads Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bursts are initiated with a Read command. The starting column and bank addresses are provided with the Read command and Auto Precharge is either enabled or disabled for that burst access. If Auto Precharge is enabled, the row that is accessed starts precharge at the completion of the burst, provided tRAS has been satisfied.
  • Page 78 Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8) CONFIDENTIAL – DO NOT COPY Page 8-46 File No. SG-0184...
  • Page 79 Read Command Writes Write bursts are initiated with a Write command, as shown in timing figure Write Command on following: The starting column and bank addresses are provided with the Write command, and Auto Precharge is either enabled or disabled for that access. If Auto Precharge is enabled, the row being accessed is precharged at the completion of the burst.
  • Page 80 Data for any Write burst may be concatenated with or truncated with a subsequent Write command. In either case, a continuous flow of input data can be maintained. The new Write command can be issued on any positive edge of clock following the previous Write command. The first data element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated.
  • Page 81 Data Input (Write) Data Output (Read) WM8776 Application The WM8776 is a high performance, stereo audio codec with five channel input selector. The WM8776 is ideal for surround sound processing applications for home hi-fi, DVD-RW and other audiovisual equipment. Etch ADC channel has programmable gain control with automatic level control.
  • Page 82 BLOCK DIAGRAM 1. Audio sample rate The master clock forWM8776 supports DAC and ADC audio sampling rates 256fs to 768fs, where fs is the audio sample frequency (DACLRC or ADCLRC) typically 32KHZ, 44.1KHZ, 48KHZ or 96KHZ (the DAC also supports operation at 128fs and 192fs and 192KHZ sample rate).
  • Page 83 2. DIGITAL AUDIO INTERFACE a. Slave mode The audio interfaces operations in either slave mode selectable using the MS control bit. In slave mode DIN is always an input to the WM8776 and DOUT is always an output. The default is Slave mode.
  • Page 84 b. 2 Wire serial control mode The wm8776 supports software control via a 2-wire serial bus. Many devices can be controlled by the same bus, and each device has a uni ue 7-bit address (this is not the same as the 7-bit address of each register in the wm8776).
  • Page 85 Sil9011 Application The sil9011 provides a complete solution for receiving HDMI compliant digital audio and video. Specialized audio and video processing is available within the sil9011 to easily and cost effectively adds HDMI capability to consumer electronics devices such as digital TVs, plasma displays, LCD TVs and projectors.
  • Page 86 1. TMDS Digital Core The core performs 10-to-8-bit TMDS decoding on the audio and video received from the three TMDS differential data lines along with a TMDS differential clock. The TMDS core supports link clock rates to 165MHZ, including CE modes to 720P/1080I/1080P. 2.
  • Page 87 The receiver can also process the video data before it is output as show below figure 5. I c Interface to Display Controller The Controller I c interface (CSDA, CSCL) on the sil9011 is a slave interface capable of running up to 400KHZ. This bus is used to configure the SIL9011 by reading/writing to the appropriate registers.
  • Page 88 BLOCK DIAGRAM 1. I c Bus I2C BUS is interring bus system controlled by 2 lines (SDA, SCL). Data are transmitted and received in the units of byte and Acknowledge. It is transmitted by MSB first from the Start conditions. The data format is set as shown in the following figure.
  • Page 89 2. Switch control table a. Video output 1 b. Audio output 1 c. Audio gain CONFIDENTIAL – DO NOT COPY Page 8-57 File No. SG-0184...
  • Page 90 TDA8946 Application In L32 TV the TDA8946AJ is a dual-channel audio power amplifier with DC gain control. It has an output power of 2  　10 W at an 8 Block diagram 1. Input configuration The TDA8946AJ inputs can be driven symmetrical (floating) as well as asymmetrical. In the asymmetrical mode one input pin is connected via a capacitor to the signal source and the other input is connected to the signal ground.
  • Page 91 2. Output power measurement The output power as a function of the supply voltage is measured on the output pins at THD = 10%,in the L32 LCD TV Vcc=12V so we can see as shown in the following figure output about CONFIDENTIAL –...
  • Page 92 3. Mode selection In the L32 LCD TV TDA8946AJ has two functional modes, which can be selected by applying the proper DC voltage to pin MODE. In this mode the amplifier is DC-biased but not operational (no audio output). a. Mute — This allows the input coupling capacitors to be charged to avoid pop-noise.

  • Page 93: Waveforms

    Chapter 9 Waveforms Main Board 1. Voltage Measurement (1) 12V (DV120B, U6-1) (2) 9V (AV_V90, U6-3) CONFIDENTIAL – DO NOT COPY Page 9-1 File No. SG-0184...
  • Page 94 (3) 5V (DV50A, CB15) (4) 3.3V (DV33A, U5-3) CONFIDENTIAL – DO NOT COPY Page 9-2 File No. SG-0184...
  • Page 95 (5) 2.5V (DV25, CE42) (6) 1.8V (DV18A, U5-2) CONFIDENTIAL – DO NOT COPY Page 9-3 File No. SG-0184...
  • Page 96 2. Clock Timing (1) MT8205 Clock (Ch1 U9-A15, XTALI / Ch2 U9-B15, XTALO) (2) Memory Clock (Ch1 U11-45, D_CLK / Ch2 U12-45, D_CLK) CONFIDENTIAL – DO NOT COPY Page 9-4 File No. SG-0184...
  • Page 97 (3) Sil 9011 Clock (Ch1 U16-85, XTLI / Ch2 U16-84, XTLO) CONFIDENTIAL – DO NOT COPY Page 9-5 File No. SG-0184...
  • Page 98 3. H-sync & V-sync Timing (1) PC Mode (1024 x 768 60Hz) Ch1 H-sync (FB46) / Ch2 V-sync (FB45) CONFIDENTIAL – DO NOT COPY Page 9-6 File No. SG-0184...
  • Page 99 ATSC Board 1. Voltage Measurement (1) 12V (+12V, C4) (2) 5V (+5V, C239) CONFIDENTIAL – DO NOT COPY Page 9-7 File No. SG-0184...
  • Page 100 (3) 3.3V (DV33, C11) (4) 2.5V (DV25, C185) CONFIDENTIAL – DO NOT COPY Page 9-8 File No. SG-0184...
  • Page 101 (5) 1.8V (DV18, C64) (6) 1.25V (+1V25_DDR, C148) CONFIDENTIAL – DO NOT COPY Page 9-9 File No. SG-0184...
  • Page 102 (7) 1.2V (DV12, C26) CONFIDENTIAL – DO NOT COPY Page 9-10 File No. SG-0184...
  • Page 103 2. Clock Timing (1) MT5351 Clock Timing (U10 B2-OXTALI) (2) MT5111 Clock Timing (U9 97-XTAL1 / 96-XTAL2) Ch1 – XTAL1 / Ch2 – XTAL2 CONFIDENTIAL – DO NOT COPY Page 9-11 File No. SG-0184...
  • Page 104 (3) Memory Clock Timing (U13-45, MEM_CLKA) (4) Memory Clock Timing (U12-45, MEM_CLKA) CONFIDENTIAL – DO NOT COPY Page 9-12 File No. SG-0184...

  • Page 105: Trouble Shooting

    Chapter 10 MONITOR DISPLAY NOTHING (PC MODE) LED is lighted LED is lighting? U9 no data out? U9 no data in? Check P3 D-sub Input correct CONFIDENTIAL – DO NOT COPY Trouble shooting Start Is Power board output +5V? Is J1 connector good? Is DC-DC OK? Is U4 (3.3V) working ok? It is in power saving...
  • Page 106 (TV, COMPOSITE VIDEO1, 2, 3, S-VIDEO) IS NOT DISPLAY CORRECTLY Start Input signal U20 input U20 output LVDS output 1.Chcak J6 Connect is good? 2.Is panel working ok? CONFIDENTIAL – DO NOT COPY 1.Check video 2.Check DVD player 1.Check P2 signal 2.Check signal between P2 and U20 (IF AV1/AV2 mode)
  • Page 107 (COMPONENT1, 2) IS NOT DISPLAY CORRECTLY Input signal U21 input U9 input LVDS output 1.Is J6 connected CONFIDENTIAL – DO NOT COPY Start good? 1.Check video 2.Check host’s setting 1.Check signal between P8&U21 1.Check signal between U21&U9 2.Check U9 Clock (27MHZ) 1.Check U9 2.Check U9 power 3.3V 1.8V...
  • Page 108 (HDMI) IS NOT DISPLAY CORRECTLY Input signal U16 input U16 no data 1.Is J6 connected good? 2.Is panel working ok? CONFIDENTIAL – DO NOT COPY Start 1.Check video 2.Check host’s setting 1.Check p1 connect 2.Check signal between P1 and U16 1.Check U16 power 2.Check between signal U16 and U9...
  • Page 109 TROUBLE OF DC-DC CONVERTER J1 PIN 9,10,11 J1 PIN 2,3,4,5 U7 pin 5 6 7 8 CONFIDENTIAL – DO NOT COPY Start U4 pin2 U6 pin 3 U14 pin2 U5 pin2 U13 pin2 The voltage is about + 5V 1.Check power board 2.Check power cable connection J1 The voltage is about + 12V...
  • Page 110 TROUBLE OF DDC READING Analog DDC HDMIDDC CONFIDENTIAL – DO NOT COPY Start Support DDC1/2B 1.Analog cable ok? 2.Check signal (U18 to P3) 3.Check U18 Voltage 4.Is compliant protocol? Support DDC1/2B 1.Analog cable ok? 2.Check signal (U17 to P1) 3.Check U17 Voltage 4.Is compliant protocol? Page 10-6 File No.

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