Memory Mapped I/O; Tape I/O - Alesis MMT-8 Service Manual

This circuit uses the differential between raw +10V, and regulated +5V, to generate the
required signals for system RESET. This is necessary due to fact that the system MUST be in a
reset state while powering down, otherwise, random noise on the 8031 data, and address, busses
could corrupt SRAM data, and destroy any hope that the battery backup will work. R11, R12, and
the 5.1V zener diode (D1), work together as a voltage divider to the base of Q1, and is designed so
that transistor Q1 will turn on when the raw +10V supply is roughly 7V. This is to ensure that
RESET does not occur until after the +5V regulator is fully functioning (i.e. +5V rail is solid). If
RESET occurs too early, noise on the +5V rail can cause data corruption. Before the Q1 turn on
threshold, Q2 remains turned on (the base of the transistor being pulled up by R13). This in turn
holds the voltage across C8 at .3 volts. This is below the threshold (set by R17 and R18) necessary
to turn on the comparator U14A, leaving the reset line high (pulled up by R14). Once the raw supply
has reached a sufficient level to turn on Q1 (roughly 7V), Q1 will pull the base of Q2 low, turning it
off. This allows C8 to begin charging through R15. Once C8 has charged to roughly 3.3V, the
comparator will switch states pulling the input of the inverter (U14A) high (thus switching the
invertors output low). This in turn pulls the threshold voltage of the comparator down to 1.6V,
ensuring that noise does not cause any false resets. This completes the reset cycle during power
up.
During power down, the opposite occurs, ensuring that the 8031 is held in a reset state
during power down as well. This is necessary in order to prevent random data from being written
into the SRAM during shutdown. Be aware that this can cause unusual unit lockups to occur if the
circumstances are just right. For example, if an MMT-8 was shut off while in record mode, it's
possible the 8031 was put into reset in the middle of writing a two byte pointer into memory. If only
one of those bytes is written before reset, then it may point to an incorrect location in memory
(battery backup holds the incorrect data). When the unit is powered back up, the incorrect pointer
may send the software into "never never land" where the only way to recover is to reinitialize the
unit.

3.20 Memory Mapped I/O

In order to easily control the vast number of hardware functions that the 8031 needs to
access, a system of memory mapped I/O is used. The basic idea is to make hardware functions
appear to the 8031 as unused memory locations. That way all that the software has to do is write to
an unused memory location in order to send that information to a specific device such as the LCD,
or keypad LEDs.
74HC138 (U13) performs the majority of the work in this circuit. Two things are
required before U13 becomes active. 1> A15 must be low (i.e. the 8031 is accessing the lower 32K
of address space). 2> The 8031 WRite line must be active (the 8031 is performing a memory write).
A15 is used to directly control which function (memory or I/O) is active.
Once U13 is enabled, addresses A8-A10 are decoded by it, and the latch corresponding to
the value of the decoded address is strobed. At this point, data on the 8031 data buss is "written"
into the latch.

4.00 Tape I/O

Tape output is very simple, while tape input is somewhat more complicated. This is due to
fact tape backup and tape sync have different requirements. It's important to remember that not all
tape decks are created equal. Probably the largest factor involved is the decks input and output
capacitances. These can greatly affect the signals sent to and from the deck, and may cause some
decks to be incompatible with the tape I/O needs of the MMT-8. However, these cases should be
rare, as the components chosen for the MMT-8 are based on the industry "standards" that most
manufacturers adhere to.
Alesis MMT-8 Service Manual 1.00
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