Motorola M68HC08 Designer Reference Manual page 16

USB and PS/2 Multimedia Keyboard Interface
1.5.3 PS/2 Protocol
Register POCR
Bit PTE4P
PTE4
Interrupt —
Enabled
Release
Data/Clock 1
High
Drive
Data/Clock —
Low
1.5.4 Host to Device Communications
Designer Reference Manual
16
Freescale Semiconductor, Inc.
The PS/2 is a bidirectional serial interface using two signals: Clock and
Data. The data consists of 11 bits including 1 start bit, 8 data bits, 1 odd
parity bit, and 1 stop bit. PS/2 device generates the clock signal with a
typical cycle of 80µs in both host-to-device or device-to-host
communications.
Table 1-1. Clock and Data Line Control
Register Bits
PTE DDRE IOCR
PTE4 DDRE4 PTE4IE
— —
— 0
0 1
Table 1-1 shows the setting of the registers for controlling the PTE3
(Clock) and the PTE4 (Data) pins. Instead of setting DDR3/DDR4 as
high to output a high signal, we set DDR3/DDR4 as an input with internal
pullup to perform the same function. In the PS/2 routines, the values of
PTE3 and PTE4 are cleared to zero and the values of PTE3P and
PTE4P are set to one. Set DDR3 or DDR4 to one to force it as output
low, or clear DDR3 or DDR4 to zero to make it high impedance and
pulled high by the 5K internal resistor.
Data sent from host to device is read while the clock line is high. In an
idle state, both the Clock and the Data lines are pulled high. The host
starts sending data by pulling the Clock line low for a minimum of 100ms.
Figure 1-9 shows the signal diagram. Communications steps are shown
as below:
1. Host waits until no auxiliary device transmission is in progress.
USB and PS/2 Multimedia Keyboard Interface
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POCR PTE
PTE3P PTE3
1 — —
— 1 —
— — 0
Port Pins
PTE4 PTE3
DDRE
(Data) (Clock)
PTE4 PTE3
DDRE3
(Data) (Clock)
Input
— —
High
Input Input
0
High High
Output Output
1
Low Low
DRM014 — Rev 0
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