Usb Controller With Host And Peripheral Ports - Xilinx ML50 Series User Manual

R
settings (See
whether the PHY defaults to RGMII mode (pin 2-3) or GMII mode (pin 1-2).
Table 1-13: Board Connections for PHY Configuration Pins
Connection on
Config Pin
Board
CONFIG0 V 2.5V
CC
CONFIG1 Ground
CONFIG2 V 2.5V
CC
CONFIG3 V 2.5V
CC
V 2.5V or
CC
CONFIG4 LED_DUPLEX
(Set by J40)
CONFIG5 V 2.5V
CC
CONFIG6 LED_RX

22. USB Controller with Host and Peripheral Ports

A Cypress CY7C67300 embedded USB host controller provides USB connectivity for the
board. The USB controller supports host and peripheral modes of operation. The USB
controller has two serial interface engines (SIE) that can be used independently. SIE1 is
connected to the USB Host connector (P19). SIE2 is connected only to the USB Peripheral
connector (P17).
The USB controller has an internal microprocessor to assist in processing USB commands.
The firmware for this processor can be stored in its own dedicated IIC EEPROM (U28) or
can be downloaded from a host computer via a peripheral connector. The USB controller's
serial port is connected to J30 through an RS-232 transceiver to assist with debug. Jumper
J50 can be installed to prevent the USB controller from executing firmware stored in the IIC
EEPROM.
ML501 Evaluation Platform
UG226 (v1.3) November 10, 2008
Table 1-13). These settings can be overwritten via software. Jumper J40 selects
Bit[2]
Definition and Value
PHYADR[2] = 1
ENA_PAUSE = 0
ANEG[3] = 1
ANEG[0] = 1
HWCFG_MODE[2] = 0 or 1
(Set by J40)
DIS_FC = 1
SEL_BDT = 0
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Bit[1]
Definition and Value
PHYADR[1] = 1
PHYADR[4] = 0
ANEG[2] = 1
ENA_XC = 1
HWCFG_MODE[1] = 1
DIS_SLEEP = 1
INT_POL = 1
Detailed Description
Bit[0]
Definition and Value
PHYADR[0] = 1
PHYADR[3] = 0
ANEG[1] = 1
DIS_125 = 1
HWCFG_MODE[0] = 1
HWCFG_MODE[3] = 1
75/50Ω = 0
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